NXP Semiconductors UM10237

User manual Rev. 02 — 19 December 2008 481 o f 792

Chapter 18: LPC24XX CAN controllers CAN1/2

Bits 24-31 are captured when CAN arbitration is lost. At the same time, if the ALIE bit in CANIER is 1, the ALI bit in this register is set, and a CAN interrupt can occur. Once either of these bytes is captured, its value will remain the same until it is read, at which time it is released to capture a new value.The clearing of bits 1 to 10 and the releasing of bits 16-23 and 24-31 all occur on any read from CANxICR, regardless of whether part or all of the register is read. This means that software should always read CANxICR as a word, and process and deal with all bits of the register as appropriate for the application.

Table 423. Interr upt and Capture Register (CAN1ICR - address 0xE0 04400C, CAN2IC R -

address 0xE004 800C) bit description

Bit Symbol Value Function Reset

Value RM

Set

0RI

[1] 0 (reset)

1 (set) Receive Interrupt. This bit is set whenever the RBS bit

in CANxSR and the RIE bit in CANxIER are both 1,

indicating that a new message was received and

stored in the Receive Buffer.

1 TI1 0 (reset)

1 (set) Transmit Interrupt 1. This bit is set when the TBS1 bit

in CANxSR goes from 0 to 1 (whenever a message

out of TXB1 was successfully transmitted or aborted),

indicating that Transmit buffer 1 is available, and the

TIE1 bit in CANxIER is 1.

2 EI 0 (reset)

1 (set) Error Warning Interrupt. This bit is set on every

change (set or clear) of either the Error Status or Bus

Status bit in CANxSR and the EIE bit bit is set within

the Interrupt Enable Register at the time of the

change.

3 DOI 0 (reset)

1 (set) Data Overrun Interrupt. This bit is set when the DOS

bit in CANxSR goes from 0 to 1 and the DOIE bit in

CANxIER is 1.

4WUI

[2] 0 (reset)

1 (set) Wake-Up Interrupt. This bit is set if the CAN controller

is sleeping and bus activity is detected and the WUIE

bit in CANxIER is 1.

5 EPI 0 (reset)

1 (set) Error Passive Interrupt. This bit is set if the EPIE bit in

CANxIER is 1, and the CAN controller switches

between Error Passive and Error Active mode in

either direction.

This is the case when the CAN Controller has reached

the Error Passive Status (at least one error counter

exceeds the CAN protocol defined level of 127) or if

the CAN Controller is in Error Passive Status and

enters the Error Active Status again.

6 ALI 0 (reset)

1 (set) Arbitration Lost Interrupt. This bit is set if the ALIE bit

in CANxIER is 1, and the CAN controller loses

arbitration while attempting to transmit. In this case

the CAN node becomes a receiver.

7 BEI 0 (reset)

1 (set) Bus Error Interrupt -- this bit is set if the BEIE bit in

CANxIER is 1, and the CAN controller detects an error

on the bus.