UM10237_2 © NXP B.V. 2008. All rights reserved.
User manual Rev. 02 — 19 December 2008 476 o f 792
NXP Semiconductors UM10237
Chapter 18: LPC24XX CAN controllers CAN1/2
[1] During a Hardware reset or when the Bus Status bit is set '1' (Bus-Off), the Reset Mode bit is set '1' (present). After the Reset Mode bit
is set '0' the CAN Controller will wait for:
- one occurrence of Bus-Free signal (11 recessive bits), if the preceding reset has been caused by a Hardware reset or a CPU-initiated
reset.
- 128 occurrences of Bus-Free, if the preceding reset has been caused by a CAN Controller initiated Bus-Off, before re-entering the
Bus-On mode.
[2] This mode of operation forces the CAN Controller to be error passive. Message Transmission is not possible. The Listen Only Mode can
be used e.g. for software driven bit rate detection and "hot plugging".
[3] A write access to the bits MOD.1 and MOD.2 is possible only if the Reset Mode is entered previously.
[4] Transmit Priority Mode is explained in more detail in Section 18–6.3 “Transmit Buffers (TXB)”.
[5] The CAN Controller will enter Sleep Mode, if the Sleep Mode bit is set '1' (sleep), there is no bus activity, and none of the CAN interrupts
is pending. Setting of SM with at least one of the previously mentioned exceptions valid will result in a wake-up interrupt. The CAN
Controller will wake up if SM is set LOW (wake-up) or there is bus activity. On wake-up, a Wake-up Interrupt is generated. A sleeping
CAN Controller which wakes up due to bus activity will not be able to receive this message until it detects 11 consecutive recessive bits
(Bus-Free sequence). Note that setting of SM is not possible in Reset Mode. After clearing of Reset Mode, setting of SM is possible only
when Bus-Free is detected again.
[6] The LOM and STM bits can only be written if the RM bit is 1 prior to the write operation.
8.2 Command Register (CAN1CMR - 0xE004 x004, CAN2CMR - 0xE004 8004)

Writing to this write-only register initiates an action within the transfer layer of the CAN

Controller. Bits not listed should be written as 0. Reading this register yields zeroes.

At least one internal clock cycle is needed for processing between two commands.

2STM
[3][6] Self Test Mode. 0 x
0(normal) A transmitted message must be acknowledged to be considered successful.
1(self test) The controller will consider a Tx message successf ul even if there is no
acknowledgment received.
In this mode a full node test is possible without any other active node on the bus
using the SRR bit in CANxCMR.
3TPM
[4] Transmit Priority Mode. 0 x
0(CAN ID) The transmit priority for 3 Transmit Buffers depends on the CAN Identifier.
1(local prio) The transmit pr iority for 3 Transmit Buffers depends on the contents of the Tx
Priority register within the Transmit Buffer.
4SM
[5] Sleep Mode. 0 0
0(wake-up) Normal operation.
1(sleep) The CAN controller enters Sleep Mode if no CAN interrupt is pending and there
is no bus activity. See the Sleep Mode description Section 18–9.2 on page 494.
5 RPM Receive Polarity Mode. 0 x
0(low active) RD input is active Low (dominant bit = 0).
1(high active) RD input is active High (dominant bit = 1) -- reverse polarity.
6 - - Reserved, user software should not write ones to reserved bits. 0 0
7 TM Test Mode. 0 x
0(disabled) Normal operation.
1(enabled) The TD pin will reflect the bit, detected on RD pin, with the next positive edge of
the system clock.
Table 420. Mode register (CAN1MOD - address 0x E004 4000, CAN2MOD - addre ss 0xE004 8000) bit description
Bit Symbol Value Function Reset
Value RM
Set