UM10237_2 © NXP B.V. 2008. All rights reserved.
User manual Rev. 02 — 19 December 2008 30 of 792
NXP Semiconductors UM10237
Chapter 3: LPC24XX System control
Once a bit from EINT0 to EINT3 is set and an appropriate code starts to execute (handling
wakeup and/or external interrupt), this bit in EXTINT register must be cleared. Otherwise
event that was just triggered by activity on the EINT pin will not be recognized in future.
Important: whenever a change of external interrupt operating mode (i.e. active
level/edge) is performed (including the initialization of an external interrupt),
corresponding bit in the EXTINT register must be cleared! For details see Section
3–3.1.3 “External Interrupt Mode register (EXTMODE - 0xE01F C148)” and Section
3–3.1.4 “External Interrupt Polarity register (EXTPOLAR - 0xE01F C14C)”.
For example, if a system wakes up from power-down using low level on external interrupt
0 pin, its post-wakeup code must reset EINT0 bit in order to allow future entry into the
power-down mode. If EINT0 bit is left set to 1, subsequent attempt(s) to invoke
power-down mode will fail. The same goes for external interrupt handling.
More details on power-down mode will be discussed in the following chapters.
[1] Example: If the EINTx is selected to be low level sensitive and low level is present on corresponding pin,
this bit can not be cleared; this bit can be cleared only when signal on the pin becomes high.
Table 25. External Interrupt Flag register (EXTINT - address 0xE01F C140) bit description
Bit Symbol Description Reset
value
0 EINT0 In level-sensitive mode, this bit is set if the EINT0 function is selected for its
pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if
the EINT0 function is selected for its pin, and the selected edge occurs on
the pin.
This bit is cleared by writing a one to it, except in level sensitive mode when
the pin is in its active state.[1]
0
1 EINT1 In level-sensitive mode, this bit is set if the EINT1 function is selected for its
pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if
the EINT1 function is selected for its pin, and the selected edge occurs on
the pin.
This bit is cleared by writing a one to it, except in level sensitive mode when
the pin is in its active state.[1]
0
2 EINT2 In level-sensitive mode, this bit is set if the EINT2 function is selected for its
pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if
the EINT2 function is selected for its pin, and the selected edge occurs on
the pin.
This bit is cleared by writing a one to it, except in level sensitive mode when
the pin is in its active state.[1]
0
3 EINT3 In level-sensitive mode, this bit is set if the EINT3 function is selected for its
pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if
the EINT3 function is selected for its pin, and the selected edge occurs on
the pin.
This bit is cleared by writing a one to it, except in level sensitive mode when
the pin is in its active state.[1]
0
7:4 - Reserved, user software should not write ones to reserved bits. The value
read from a reserved bit is not defined. NA