UM10237_2 © NXP B.V. 2008. All rights reserved.
User manual Rev. 02 — 19 December 2008 57 of 792
NXP Semiconductors UM10237
Chapter 4: LPC24XX Clocking and power control
3.3.1 CPU Clock Configuration register (CCLKCFG - 0xE01F C104)
The CCLKCFG register controls the division of the PLL output before it is used by the
CPU. When the PLL is bypassed, the division may be by 1. When the PLL is running, the
output must be divided in order to bring the CPU clock frequency (cclk) within operating
limits. An 8 bit divider allows a range of options, including slowing CPU operation to a low
rate for temporary power savings without turning off the PLL.
Note: When the USB interface is used in an application, cclk must be at least 18 MHz in
order to support internal operations of the USB block.
The cclk is derived from the PLL output signal, divided by CCLKSEL + 1. Having
CCLKSEL = 1 results in CCLK being one half the PLL output, CCLKSEL = 3 results in
CCLK being one quarter of the PLL output, etc..
3.3.2 USB Clock Configuration register (USBCLKCFG - 0xE01F C108)
The USBCLKCFG register controls the division of the PLL output before it is used by the
USB block. If the PLL is bypassed, the division may be by 1. In that case, the PLL input
frequency must be 48 MHz, with a 500 ppm tolerance. When the PLL is running, the
output must be divided in order to bring the USB clock frequency to 48 MHz with a 50%
duty cycle. A 4-bit divider allows obtaining the correct USB clock from any even multiple of
48 MHz (i.e. any mutliple of 96 MHz) within the PLL operating range.
Remark: The Internal RC clock can not be used as a clock source for USB because a
more precise clock is needed (see Tab le 4–4 2).
[1] Actual reset value depends on IRC factory trimming.
The USB clock is derived from the PLL output signal, divided by USBSEL + 1. Having
USBSEL = 1 results in USB’s clock being one half the PLL output.
3.3.3 IRC Trim Register (IRCTRIM - 0xE01F C1A4)
This register is used to trim the on-chip 4 MHz oscillator.
Table 53. CPU Clock Configuration register (CCLKCFG - address 0xE01F C104) bit
description
Bit Symbol Description Reset
value
7:0 CCLKSEL Selects the divide value for creating the CPU clock (CCLK) from the
PLL output.
Only 0 and odd values (1, 3, 5, ..., 255) are supported and can be
used when programming the CCLKSEL bits.
Warning: Using an even value (2, 4, 6, ..., 254) when setting the
CCLKSEL bits may result in incorrect operation of the device.
0x00
Table 54. USB Clock Configuration register (USBCLKCFG - address 0xE01F C108) bit
description
Bit Symbol Description Reset
value
3:0 USBSEL Selects the divide value for creating the USB clock from the PLL output.
Warning: Improper setting of this value will result in incorrect operation
of the USB interface.
0
7:4 - Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined. NA