NXP Semiconductors UM10237 user manual 3. Tables

UM10237_2 © NXP B.V. 2008. All rights reserved.
User manual Rev. 02 — 19 December 2008 761 o f 792
NXP Semiconductors UM10237
Chapter 36: LPC24XX Supplementary information
3. Tables
Table 1. LPC24XX overview. . . . . . . . . . . . . . . . . . . . . . .3
Table 2. Differences between LPC2400 parts . . . . . . . . . 4
Table 3. LPC2458 ordering information . . . . . . . . . . . . . .6
Table 4. LPC2458 ordering options . . . . . . . . . . . . . . . . . 6
Table 5. LPC2420/60 ordering information . . . . . . . . . . .6
Table 6. LPC2420/60 ordering options . . . . . . . . . . . . . . 7
Table 7. LPC2468 ordering information . . . . . . . . . . . . . .7
Table 8. LPC2468 ordering options . . . . . . . . . . . . . . . . . 7
Table 9. LPC2470 ordering information . . . . . . . . . . . . . .7
Table 10. LPC 2470 ordering options . . . . . . . . . . . . . . . . .8
Table 11. LPC 2478 ordering information . . . . . . . . . . . . . .8
Table 12. LPC 2478 ordering options . . . . . . . . . . . . . . . . .8
Table 13. LPC 2400 memory options and addressing. . . .16
Table 14. LPC 2458 memory usage and details . . . . . . . .16
Table 15. LPC 2420/60/70 memory usage and details . . .17
Table 16. LPC 2468/78 memory usage and details. . . . . .17
Table 17. APB peripherals and base addresses . . . . . . .22
Table 18. ARM except ion vector locations. . . . . . . . . . . . 23
Table 19. LPC 2400 Memory mapping modes . . . . . . . . .24
Table 20. Memory mappi ng control registers. . . . . . . . . . 25
Table 21. Memory Mappi ng cont rol register (MEMMAP -
address 0xE01F C040) bit description . . . . . . .25
Table 22. Pin summary. . . . . . . . . . . . . . . . . . . . . . . . . . .28
Table 23. Summary of system control registers . . . . . . . .28
Table 24. External Interrupt registers . . . . . . . . . . . . . . . .29
Table 25. External Interrupt Flag register (EXTINT - address
0xE01F C140) bit description. . . . . . . . . . . . . .30
Table 26. External Interrupt Mode register (EXTMODE -
address 0xE01F C148) bit description . . . . . . .31
Table 27. External Interrupt Polarity register (EXTPOLAR -
address 0xE01F C14C) bit description. . . . . . .32
Table 28. Re set Source Identification register (RSID -
address 0xE01F C180) bit description . . . . . . .35
Table 29. System Cont rols and Status register (SCS -
address 0xE01F C1A0) bit description. . . . . . . 35
Table 30. AHB conf iguration register map . . . . . . . . . . . .36
Table 31. AHB Arbiter Configuration register 1 (AHBCFG1 -
address 0xE01F C188) bit description . . . . . . .37
Table 32. Priority sequence (bit 0 = 0): LCD, CPU, GPDMA,
AHB1, USB. . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Table 33. Prio rity sequence (bit 0 = 0): USB, AHB1, CPU,
GPDMA, LCD. . . . . . . . . . . . . . . . . . . . . . . . . .38
Table 34. Prio ri ty sequence (bit 0 = 0): GPDMA, AHB1,
CPU, LCD, USB . . . . . . . . . . . . . . . . . . . . . . . .38
Table 35. Prio rity sequence (bit 0 = 0): USB, AHB1, CPU,
GPDMA, LCD. . . . . . . . . . . . . . . . . . . . . . . . . .38
Table 36. AHB Arbiter Configuration register 2 (AHBCFG2 -
address 0xE01F C18C) bit description. . . . . . .39
Table 37. Prio ri ty sequence (bit 0 = 0): Ethernet, CPU . . 39
Table 38. Prio ri ty sequence (bit 0 = 0): Ethernet, CPU . . 40
Table 39. Re comme nded values for CX1/X2 in oscillation
mode (crystal and external components
parameters) low frequency mode (OSCRANGE =
0, see Table3–29) . . . . . . . . . . . . . . . . . . . . . .44
Table 40. Re comme nded values for CX1/X2 in oscillation
mode (crystal and external components
parameters) high frequency mode (OSCRANGE =
1, see Table3–29) . . . . . . . . . . . . . . . . . . . . . . 44
Table 41. Summary of system control registers . . . . . . . .45
Table 42. Clock Source Select re gister (CLKSRCSEL -
address 0xE01F C10C) bit description . . . . . .46
Table 43. PLL registers . . . . . . . . . . . . . . . . . . . . . . . . . .48
Table 44. PLL Control regi ster (PLLCON - address
0xE01F C080) bit description. . . . . . . . . . . . . .48
Table 45. PL L Configuration register (PLLCFG - address
0xE01F C084) bit description. . . . . . . . . . . . . .49
Table 46. Mul tiplier values for a 32kHz oscil lator . . . . . . 49
Table 47. PL L Status register (PLLSTAT - address
0xE01F C088) bit description. . . . . . . . . . . . . .51
Table 48. PLL control bit combinations . . . . . . . . . . . . . . 52
Table 49. PL L Feed register (PLLFEED - address
0xE01F C08C) bit description . . . . . . . . . . . . . 52
Table 50. PLL frequency parameter . . . . . . . . . . . . . . . . 53
Table 51. Addit ional Multiplier Values for use with a Low
Frequency Clock Input. . . . . . . . . . . . . . . . . . . 53
Table 52. Po tential values for PLL example . . . . . . . . . . 55
Table 53. CPU Cl ock Conf iguration register (CCLKCFG -
address 0xE01F C104) bit description. . . . . . . 57
Table 54. USB Clock Configuration register (USBCLKCFG -
address 0xE01F C108) bit description. . . . . . . 57
Table 55. I RC Trim register (IRCTRIM - address
0xE01F C1A4) bit description . . . . . . . . . . . . . 58
Table 56. Peripheral Clock Selection register 0 (PCLKSEL0
- address 0xE01F C1A8) bit description . . . . . 58
Table 57. Peripheral Clock Selection register 1 (PCLKSEL1
- address 0xE01F C1AC) bit description . . . . . 58
Table 58. Peri phe ral Clock Selection register bit values . 59
Table 59. Power Control registers . . . . . . . . . . . . . . . . . . 61
Table 60. Po wer Mode Control register (PCON - address
0xE01F C0C0) bit description . . . . . . . . . . . . . 61
Table 61. Encoding of reduced power modes . . . . . . . . . 62
Table 62. Interrup t Wakeup register (INTWAKE - address
0xE01F C144) bit description. . . . . . . . . . . . . .63
Table 63. Po wer Control for Peripherals register (PCONP -
address 0xE01F C0C4) bit description . . . . . .64
Table 64. EMC configuration . . . . . . . . . . . . . . . . . . . . . . 67
Table 65. Memory bank selection . . . . . . . . . . . . . . . . . .72
Table 66. Pad interface and control signal descriptions . 73
Table 67. Summary of EMC registers . . . . . . . . . . . . . . . 74
Table 68. EMC Control register (EMCControl - address
0xFFE0 8000) bit description. . . . . . . . . . . . . . 76
Table 69. EMC Status register (EMCStatus - address
0xFFE0 8008) bit description. . . . . . . . . . . . . . 77
Table 70. EMC Configurat ion register (EMCConfig -
address 0xFFE0 8008) bit description. . . . . . . 78
Table 71. Dynamic Control regi ster (EMCDynamicControl -
address 0xFFE0 8020) bit description. . . . . . . 78
Table 72. Dyn amic Memory Refresh Timer register
(EMCDynamicRefresh - address 0xFFE0 8024)
bit description. . . . . . . . . . . . . . . . . . . . . . . . . .80
Table 73. Dyn amic Memory Read Configuration register
(EMCDynamicReadConfig - address