Main
UM10237
LPC24XX User manual
Rev. 02 19 December 2008 User manual
Contact information
1. Introduction
2. How to read this manual
UM10237
Chapter 1: LPC24XX Introductory information
3. LPC2400 features
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functions.
5. Ordering options
5.1 LPC2458 ordering options
5.2 LPC2460 ordering options
NXP Semiconductors UM10237
5.3 LPC2468 ordering options
5.4 LPC2470 ordering options
5.5 LPC2478 ordering options
6. Architectural overview
7. On-chip flash programming memory (LPC2458/68/78)
NXP Semiconductors UM10237
8. On-chip SRAM
9. LPC2458 block diagram
Fig 1. LPC2458 block diagram
LPC2458
10. LPC2420/60 block diagram
(1) LPC2460 only.
Fig 2. LPC2460 block diagram
LPC2420/2460
11. LPC2468 block diagram
Fig 3. LPC2468 block diagram
LPC2468
12. LPC2470 block diagram
Fig 4. LPC2470 block diagram
LPC2470
13. LPC2478 block diagram
Fig 5. LPC2478 block diagram
LPC2478
2. Memory map and peripheral addressing
Chapter 2: LPC24XX Memory mapping
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3. Memory maps
User manual Rev. 02 19 December 2008 19 of 792
Fig 6. LPC2400 system memory map
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(1) LPC247x only.
Fig 8. AHB peripheral map
4. APB peripheral addresses
NXP Semiconductors UM10237
5. LPC2400 memory re-mapping and boot ROM
5.1 Memory map concepts and operating modes
5.2 Memory re-mapping
6. Memory mapping control
6.1 Memory Mapping Control Register (MEMMAP - 0xE01F C040)
6.2 Memory mapping control usage notes
Fig 9. Map of lower memory is showing re-mapped and re-mappable areas for a LPC2400 part with flash
7. Prefetch abort and data abort exceptions
1. Summary of system control block functions
2. Pin description
Chapter 3: LPC24XX System control
3.1 External interrupt inputs
3.1.1 Register description
3.1.2 External Interrupt flag register (EXTINT - 0xE01F C140)
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3.1.3 External Interrupt Mode register (EXTMODE - 0xE01F C148)
3.1.4 External Interrupt Polarity register (EXTPOLAR - 0xE01F C14C)
3.2 Reset
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3.2.1 Reset Source Identification Register (RSIR - 0xE01F C180)
3.3 Other system controls and status flags
3.3.1 System Controls and Status register (SCS - 0xE01F C1A0)
3.4 AHB Configuration
3.4.1 AHB Arbiter Configuration register 1 (AHBCFG1 - 0xE01F C188)
NXP Semiconductors UM10237
3.4.2 AHB Arbiter Configuration register 2 (AHBCFG2 - 0xE01F C18C)
3.4.2.1 Examples of AHB2 settings
4. Brown-out detection
5. Code security vs. debugging
1. Summary of clocking and power control functions
Chapter 4: LPC24XX Clocking and power control
Fig 12. Clock generation for the LPC2400
ARM7 TDMI-S
2. Oscillators
2.1 Internal RC oscillator
2.2 Main oscillator
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2.3 RTC oscillator
3.1 Clock source selection multiplexer
3.1.1 Clock Source Select register (CLKSRCSEL - 0xE01F C10C)
3.2 PLL (Phase Locked Loop)
3.2.1 PLL operation
3.2.2 PLL and startup/boot code interaction
3.2.3 PLL register description
3.2.4 PLL Control register (PLLCON - 0xE01F C080)
3.2.5 PLL Configuration register (PLLCFG - 0xE01F C084)
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3.2.6 PLL Status register (PLLSTAT - 0xE01FC088)
3.2.7 PLL Interrupt: PLOCK
3.2.8 PLL Modes
3.2.9 PLL Feed register (PLLFEED - 0xE01F C08C)
3.2.10 PLL and Power-down mode
3.2.11 PLL frequency calculation
3.2.12 Procedure for determining PLL settings
3.2.13 Examples of PLL settings
3.2.14 PLL setup sequence
3.3 Clock dividers
3.3.1 CPU Clock Configuration register (CCLKCFG - 0xE01F C104)
3.3.2 USB Clock Configuration register (USBCLKCFG - 0xE01F C108)
3.3.3 IRC Trim Register (IRCTRIM - 0xE01F C1A4)
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3.4 Power control
3.4.1 Idle mode
3.4.2 Sleep mode
3.4.3 Power-down mode
3.4.4 Peripheral power control
3.4.5 Power control register description
The Power Control function uses registers shown in Table459. More detailed descriptions follow.
3.4.6 Power Mode Control register (PCON - 0xE01F C0C0)
Reduced power modes are controlled via the PCON register, as described in Table 4 60 .
3.4.7 Interrupt Wakeup Register (INTWAKE - 0xE01F C144)
3.4.8 Power Control for Peripherals register (PCONP - 0xE01F C0C4)
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3.4.9 Power control usage notes
4. Power domains
5. Wakeup timer
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Chapter 5: LPC24XX External Memory Controller (EMC)
5. EMC functional description
5.1 AHB slave register interface
5.2 AHB slave memory interface
5.2.1 Memory transaction endianness
5.2.2 Memory transaction size
5.2.3 Write protected memory areas
5.3 Pad interface
6. Low-power operation
6.1 Low-power SDRAM Deep-sleep Mode
6.2 Low-power SDRAM partial array refresh
7. Memory bank select
8. Reset
9. Pin description
10. Register description
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10.1 EMC Control register (EMCControl - 0xFFE0 8000)
10.2 EMC Status register (EMCStatus - 0xFFE0 8004)
10.3 EMC Configuration register (EMCConfig - 0xFFE0 8008)
10.4 Dynamic Memory Control register (EMCDynamicControl - 0xFFE0 8020)
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10.5 Dynamic Memory Refresh Timer register (EMCDynamicRefresh - 0xFFE0 8024)
10.6 Dynamic Memory Read Configuration register (EMCDynamicReadConfig - 0xFFE0 8028)
10.7 Dynamic Memory Percentage Command Period register (EMCDynamictRP - 0xFFE0 8030)
10.8 Dynamic Memory Active to Precharge Command Period register (EMCDynamictRAS - 0xFFE0 8034)
10.9 Dynamic Memory Self-refresh Exit Time register (EMCDynamictSREX - 0xFFE0 8038)
10.10 Dynamic Memory Last Data Out to Active Time register (EMCDynamictAPR - 0xFFE0 803C)
10.11 Dynamic Memory Data-in to Active Command Time register (EMCDynamictDAL - 0xFFE0 8040)
10.12 Dynamic Memory Write Recovery Time register (EMCDynamictWR - 0xFFE0 8044)
10.13 Dynamic Memory Active to Active Command Period register (EMCDynamictRC - 0xFFE0 8048)
10.14 Dynamic Memory Auto-refresh Period register (EMCDynamictRFC - 0xFFE0 804C)
10.15 Dynamic Memory Exit Self-refresh register (EMCDynamictXSR - 0xFFE0 8050)
10.16 Dynamic Memory Active Bank A to Active Bank B Time register (EMCDynamictRRD - 0xFFE0 8054)
10.17 Dynamic Memory Load Mode register to Active Command Time (EMCDynamictMRD - 0xFFE0 8058)
10.18 Static Memory Extended Wait register (EMCStaticExtendedWait - 0xFFE0 8080)
10.19 Dynamic Memory Configuration registers (EMCDynamicConfig0-3 - 0xFFE0 8100, 120, 140, 160)
Address mappings that are not shown in Table 587 are reserved.
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10.21 Static Memory Configuration registers (EMCStaticConfig0-3 - 0xFFE0 8200, 220, 240, 260)
10.22 Static Memory Write Enable Delay registers (EMCStaticWaitWen0-3 - 0xFFE0 8204, 224, 244 ,264)
10.24 Static Memory Read Delay registers (EMCStaticWaitRd0-3 - 0xFFE0 820C, 22C, 24C, 26C)
10.26 Static Memory Write Delay registers (EMCStaticWaitwr0-3 - 0xFFE0 8214, 234, 254, 274)
10.27 Static Memory Turn Round Delay registers (EMCStaticWaitTurn0-3 - 0xFFE0 8218, 238, 258, 278)
11. External memory interface
11.1 32-bit wide memory bank connection
a. 32 bit wide memory bank interfaced to four 8 bit memory chips
b. 32 bit wide memory bank interfaced to two 16 bit memory chips
11.2 16-bit wide memory bank connection
a. 16 bit wide memory bank interfaced to two 8 bit memory chips
11.3 8-bit wide memory bank connection
Fig 18. 8 bit bank external memory interface (bits MW = 00)
11.4 Memory configuration example
Fig 19. Typical memory configuration diagram
3. Operation
Chapter 6: LPC24XX Memory Accelerator Module (MAM)
4. Memory Acceleration Module blocks
NXP Semiconductors UM10237
4.2 Instruction latches and data latches
4.3 Flash programming Issues
5. Memory Accelerator Module operating modes
6. MAM configuration
7.1 MAM Control Register (MAMCR - 0xE01F C000)
7.2 MAM Timing Register (MAMTIM - 0xE01F C004)
Chapter 6: LPC24XX Memory Accelerator Module (MAM)
8. MAM usage notes
Chapter 6: LPC24XX Memory Accelerator Module (MAM)
2. Description
Chapter 7: LPC24XX Vectored Interrupt Controller (VIC)
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3.1 Software Interrupt Register (VICSoftInt - 0xFFFF F018)
3.2 Software Interrupt Clear Register (VICSoftIntClear - 0xFFFF F01C)
3.3 Raw Interrupt Status Register (VICRawIntr - 0xFFFF F008)
3.4 Interrupt Enable Register (VICIntEnable - 0xFFFF F010)
3.5 Interrupt Enable Clear Register (VICIntEnClear - 0xFFFF F014)
3.6 Interrupt Select Register (VICIntSelect - 0xFFFF F00C)
3.7 IRQ Status Register (VICIRQStatus - 0xFFFF F000)
3.8 FIQ Status Register (VICFIQStatus - 0xFFFF F004)
3.9 Vector Address Registers 0-31 (VICVectAddr0-31 - 0xFFFF F100 to 17C)
3.10 Vector Priority Registers 0-31 (VICVectPriority0-31 - 0xFFFF F200 to 27C)
3.11 Vector Address Register (VICAddress - 0xFFFF FF00)
3.12 Software Priority Mask Register (VICSWPriorityMask - 0xFFFF F024)
3.13 Protection Enable Register (VICProtection - 0xFFFF F020)
4. Interrupt sources
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Fig 22. Block diagram of the Vectored Interrupt Controller
2. LPC2400 pin packages
2.1 LPC2400 180-pin package
Chapter 8: LPC24XX Pin configuration
2.2 LPC2400 208-pin packages
3. LPC2458 pinning information
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4. LPC2460/68 pinning information
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5. LPC2470/78 pinning information
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6. LPC2460/70 boot control
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2. Description
Chapter 9: LPC24XX Pin connect
3. Pin function select register values
4. Pin mode select register values
5.1 Pin Function Select register 0 (PINSEL0 - 0xE002 C000)
5.2 Pin Function Select Register 1 (PINSEL1 - 0xE002 C004)
5.3 Pin Function Select register 2 (PINSEL2 - 0xE002 C008)
5.4 Pin Function Select Register 3 (PINSEL3 - 0xE002 C00C)
5.5 Pin Function Select Register 4 (PINSEL4 - 0xE002 C010)
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5.6 Pin Function Select Register 5 (PINSEL5 - 0xE002 C014)
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5.7 Pin Function Select Register 6 (PINSEL6 - 0xE002 C018)
5.8 Pin Function Select Register 7 (PINSEL7 - 0xE002 C01C)
5.9 Pin Function Select Register 8 (PINSEL8 - 0xE002 C020)
5.10 Pin Function Select Register 9 (PINSEL9 - 0xE002 C024)
5.11 Pin Function Select Register 10 (PINSEL10 - 0xE002 C028)
5.12 Pin Function Select Register 11 (PINSEL11 - 0xE002 C02C)
This register is used to select the LCD function and the LCD mode on the LPC247x.
5.13 Pin Mode select register 0 (PINMODE0 - 0xE002 C040)
This register controls pull-up/pull-down resistor configuration for PORT0 pins 0 to 15.
5.14 Pin Mode select register 1 (PINMODE1 - 0xE002 C044)
5.15 Pin Mode select register 2 (PINMODE2 - 0xE002 C048)
5.16 Pin Mode select register 3 (PINMODE3 - 0xE002 C04C)
5.17 Pin Mode select register 4 (PINMODE4 - 0xE002 C050)
5.18 Pin Mode select register 5 (PINMODE5 - 0xE002 C054)
5.19 Pin Mode select register 6 (PINMODE6 - 0xE002 C058)
5.20 Pin Mode select register 7 (PINMODE7 - 0xE002 C05C)
5.21 Pin Mode select register 8 (PINMODE8 - 0xE002 C060)
5.22 Pin Mode select register 9 (PINMODE9 - 0xE002 C064)
3.1 Digital I/O ports
Chapter 10: LPC24XX General Purpose Input/Output (GPIO)
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6.5 Fast GPIO port Mask register FIOMASK(FIO[0/1/2/3/4]MASK - 0x3FFF C0[1/3/5/7/9]0)
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6.6 GPIO interrupt registers
The following registers configure the pins of port 0 and port 2 to generate interrupts.
6.6.1 GPIO overall Interrupt Status register (IOIntStatus - 0xE002 8080)
Each bit in these read-write registers enables the rising edge interrupt for the
Each bit in these read-write registers enables the falling edge interrupt for the
6.6.6 GPIO Interrupt Clear register (IO0IntClr - 0xE002 808C and IO2IntClr - 0xE002 80AC)
Writing a 1 into each bit in these write-only registers clears any interrupts for the
7. GPIO usage notes
7.1 Example 1: sequential accesses to IOSET and IOCLR affecting the same GPIO pin/bit
7.2 Example 2: an instantaneous output of 0s and 1s on a GPIO port
7.3 Writing to IOSET/IOCLR vs. IOPIN
7.4 Output signal frequency considerations when using the legacy and enhanced GPIO registers
Chapter 11: LPC24XX Ethernet
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5. Ethernet architecture
5.1 Partitioning
5.2 Example PHY Devices
5.3 DMA engine functions
5.4 Overview of DMA operation
5.5 Ethernet Packet
6. Pin description
Fig 27. Ethernet packet fields
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7.1 Ethernet MAC register definitions
This section defines the bits in the individual registers of the Ethernet block register map.
7.1.1 MAC Configuration Register 1 (MAC1 - 0xFFE0 0000)
7.1.2 MAC Configuration Register 2 (MAC2 - 0xFFE0 0004)
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7.1.3 Back-to-Back Inter-Packet-Gap Register (IPGT - 0xFFE0 0008)
7.1.4 Non Back-to-Back Inter-Packet-Gap Register (IPGR - 0xFFE0 000C)
7.1.5 Collision Window / Retry Register (CLRT - 0xFFE0 0010)
7.1.6 Maximum Frame Register (MAXF - 0xFFE0 0014)
7.1.7 PHY Support Register (SUPP - 0xFFE0 0018)
Unused bits in the PHY support register should be left as zeroes.
7.1.8 Test Register (TEST - 0xFFE0 001C)
7.1.9 MII Mgmt Configuration Register (MCFG - 0xFFE0 0020)
7.1.10 MII Mgmt Command Register (MCMD - 0xFFE0 0024)
7.1.11 MII Mgmt Address Register (MADR - 0xFFE0 0028)
7.1.12 MII Mgmt Write Data Register (MWTD - 0xFFE0 002C)
7.1.13 MII Mgmt Read Data Register (MRDD - 0xFFE0 0030)
7.1.14 MII Mgmt Indicators Register (MIND - 0xFFE0 0034)
7.1.15 Station Address 0 Register (SA0 - 0xFFE0 0040)
7.1.16 Station Address 1 Register (SA1 - 0xFFE0 0044)
7.1.17 Station Address 2 Register (SA2 - 0xFFE0 0048)
7.2 Control register definitions
7.2.1 Command Register (Command - 0xFFE0 0100)
7.2.2 Status Register (Status - 0xFFE0 0104)
7.2.3 Receive Descriptor Base Address Register (RxDescriptor - 0xFFE0 0108)
7.2.4 Receive Status Base Address Register (RxStatus - 0xFFE0 010C)
7.2.5 Receive Number of Descriptors Register (RxDescriptor - 0xFFE0 0110)
7.2.6 Receive Produce Index Register (RxProduceIndex - 0xFFE0 0114)
7.2.7 Receive Consume Index Register (RxConsumeIndex - 0xFFE0 0118)
7.2.8 Transmit Descriptor Base Address Register (TxDescriptor - 0xFFE0 011C)
7.2.9 Transmit Status Base Address Register (TxStatus - 0xFFE00120)
7.2.10 Transmit Number of Descriptors Register (TxDescriptorNumber - 0xFFE0 0124)
7.2.11 Transmit Produce Index Register (TxProduceIndex - 0xFFE0 0128)
7.2.12 Transmit Consume Index Register (TxConsumeIndex - 0xFFE0 012C)
7.2.13 Transmit Status Vector 0 Register (TSV0 - 0xFFE00158)
7.2.14 Transmit Status Vector 1 Register (TSV1 - 0xFFE0015C)
7.2.15 Receive Status Vector Register (RSV - 0xFFE0 0160)
Table11220 lists the bit definitions of the RSV register.
7.2.16 Flow Control Counter Register (FlowControlCounter - 0xFFE0 0170)
7.2.17 Flow Control Status Register (FlowControlStatus - 0xFFE0 0174)
7.3 Receive filter register definitions
7.3.1 Receive Filter Control Register (RxFilterCtrl - 0xFFE0 0200)
7.3.2 Receive Filter WoL Status Register (RxFilterWoLStatus - 0xFFE00204)
7.3.3 Receive Filter WoL Clear Register (RxFilterWoLClear - 0xFFE0 0208)
NXP Semiconductors UM10237
7.3.4 Hash Filter Table LSBs Register (HashFilterL - 0xFFE0 0210)
7.3.5 Hash Filter Table MSBs Register (HashFilterH - 0xFFE0 0214)
7.4 Module control register definitions
7.4.1 Interrupt Status Register (IntStatus - 0xFFE0 0FE0)
7.4.2 Interrupt Enable Register (IntEnable - 0xFFE0 0FE4)
7.4.3 Interrupt Clear Register (IntClear - 0xFFE0 0FE8)
7.4.4 Interrupt Set Register (IntSet - 0xFFE0 0FEC)
7.4.5 Power Down Register (PowerDown - 0xFFE0 0FF4)
8. Descriptor and status formats
8.1 Receive descriptors and statuses
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8.2 Transmit descriptors and statuses
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9. Ethernet block functional description
9.1 Overview
9.2 AHB interface
9.3 Interrupts
9.4 Direct Memory Access (DMA)
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9.5 Initialization
9.6 Transmit process
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9.7 Receive process
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9.8 Transmission retry
9.9 Status hash CRC calculations
9.10 Duplex modes
9.11 IEE 802.3/Clause 31 flow control
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9.12 Half-Duplex mode backpressure
9.13 Receive filtering
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9.14 Power management
9.15 Wake-up on LAN
9.16 Enabling and disabling receive and transmit
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9.17 Transmission padding and CRC
9.18 Huge frames and frame length checking
9.19 Statistics counters
9.20 MAC status vectors
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9.23.2 Types of CPU access
9.23.3 Overall bandwidth
9.24 CRC calculation
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Chapter 12: LPC24XX LCD controller
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4.6 Monochrome STN panels
5.1 Signal usage
5.1.1 Signals used for single panel STN displays
5.1.2 Signals used for dual panel STN displays
5.1.3 Signals used for TFT displays
The signals used for TFT displays are shown in Table 12245.
6. LCD controller functional description
Fig 36. LCD controller block diagram
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Table12249 shows the structure of the data in each DMA FIFO word in RGB mode.
6.4 RAM palette
6.5 Hardware cursor
6.5.1 Cursor operation
6.5.2 Cursor sizes
6.5.3 Cursor movement
6.5.4 Cursor XY positioning
6.5.5 Cursor clipping
6.5.6 Cursor image format
Table12255 shows the buffer to pixel mapping for Cursor 0.
6.6 Gray scaler
6.7 Upper and lower panel formatters
6.8 Panel clock generator
6.9 Timing controller
6.10 STN and TFT data select
6.10.1 STN displays
6.10.2 TFT displays
6.11.1 Master bus error interrupt
6.11.2 Vertical compare interrupt
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7.1 LCD Configuration register (LCD_CFG, RW - 0xE01F C1B8)
7.2 Horizontal Timing register (LCD_TIMH, RW - 0xFFE1 0000)
7.2.1 Horizontal timing restrictions
7.3 Vertical Timing register (LCD_TIMV, RW - 0xFFE1 0004)
7.4 Clock and Signal Polarity register (LCD_POL, RW - 0xFFE1 0008)
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7.5 Line End Control register (LCD_LE, RW - 0xFFE1 000C)
7.6 Upper Panel Frame Base Address register (LCD_UPBASE, RW - 0xFFE1 0010)
7.7 Lower Panel Frame Base Address register (LCD_LPBASE, RW - 0xFFE1 0014)
7.8 LCD Control register (LCD_CTRL, RW - 0xFFE1 0018)
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7.9 Interrupt Mask register (LCD_INTMSK, RW - 0xFFE1 001C)
7.10 Raw Interrupt Status register (LCD_INTRAW, RW - 0xFFE1 0020)
7.11 Masked Interrupt Status register (LCD_INTSTAT, RW - 0xFFE1 0024)
7.12 Interrupt Clear register (LCD_INTCLR, RW - 0xFFE1 0028)
7.13 Upper Panel Current Address register (LCD_UPCURR, RW - 0xFFE1 002C)
7.14 Lower Panel Current Address register (LCD_LPCURR, RW - 0xFFE1 0030)
7.15 Color Palette registers (LCD_PAL, RW - 0xFFE1 0200 to 0xFFE1 03FC)
7.16 Cursor Image registers (CRSR_IMG, RW - 0xFFE1 0800 to 0xFFE1 0BFC)
7.17 Cursor Control register (CRSR_CTRL, RW - 0xFFE1 0C00)
7.18 Cursor Configuration register (CRSR_CFG, RW - 0xFFE1 0C04)
7.19 Cursor Palette register 0 (CRSR_PAL0, RW - 0xFFE1 0C08)
7.20 Cursor Palette register 1 (CRSR_PAL1, RW - 0xFFE1 0C0C)
7.21 Cursor XY Position register (CRSR_XY, RW - 0xFFE1 0C10)
7.22 Cursor Clip Position register (CRSR_CLIP, RW - 0xFFE1 0C14)
7.23 Cursor Interrupt Mask register (CRSR_INTMSK, RW - 0xFFE1 0C20)
7.24 Cursor Interrupt Clear register (CRSR_INTCLR, RW - 0xFFE1 0C24)
7.25 Cursor Raw Interrupt Status register (CRSR_INTRAW, RW - 0xFFE1 0C28)
7.26 Cursor Masked Interrupt Status register (CRSR_INTSTAT, RW - 0xFFE1 0C2C)
8. LCD timing diagrams
Fig 41. Horizontal timing for STN displays
(1) Signal polarities may vary for some displays.
Fig 42. Vertical timing for STN displays
Fig 43. Horizontol timing for TFT displays
9. LCD panel signal usage
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Chapter 13: LPC24XX USB device controller
4. Fixed endpoint configuration
5. Functional description
The architecture of the USB device controller is shown below in Figure 1345.
5.1 Analog transceiver
5.2 Serial Interface Engine (SIE)
5.3 Endpoint RAM (EP_RAM)
5.4 EP_RAM access control
5.5 DMA engine and bus master interface
6. Operational overview
7. Pin description
7.1 USB device usage note
8. Clocking and power management
8.1 Power requirements
8.2 Clocks
8.3 Power management support
8.4 Remote wake-up
9. Register description
9.1 Port select register
9.1.1 USB Port Select register (USBPortSel - 0xFFE0 C110)
9.2 Clock control registers
9.2.1 USB Clock Control register (USBClkCtrl - 0xFFE0 CFF4)
9.2.2 USB Clock Status register (USBClkSt - 0xFFE0 CFF8)
9.3 Device interrupt registers
9.3.1 USB Interrupt Status register (USBIntSt - 0xE01F C1C0)
9.3.2 USB Device Interrupt Status register (USBDevIntSt - 0xFFE0 C200)
9.3.3 USB Device Interrupt Enable register (USBDevIntEn - 0xFFE0 C204)
9.3.4 USB Device Interrupt Clear register (USBDevIntClr - 0xFFE0 C208)
9.3.5 USB Device Interrupt Set register (USBDevIntSet - 0xFFE0 C20C)
9.3.6 USB Device Interrupt Priority register (USBDevIntPri - 0xFFE0 C22C)
9.4 Endpoint interrupt registers
9.4.1 USB Endpoint Interrupt Status register (USBEpIntSt - 0xFFE0 C230)
9.4.2 USB Endpoint Interrupt Enable register (USBEpIntEn - 0xFFE0 C234)
9.4.3 USB Endpoint Interrupt Clear register (USBEpIntClr - 0xFFE0 C238)
9.4.4 USB Endpoint Interrupt Set register (USBEpIntSet - 0xFFE0 C23C)
9.4.5 USB Endpoint Interrupt Priority register (USBEpIntPri - 0xFFE0 C240)
9.5 Endpoint realization registers
9.5.1 EP RAM requirements
9.5.2 USB Realize Endpoint register (USBReEp - 0xFFE0 C244)
9.5.3 USB Endpoint Index register (USBEpIn - 0xFFE0 C248)
9.5.4 USB MaxPacketSize register (USBMaxPSize - 0xFFE0 C24C)
9.6 USB transfer registers
9.6.1 USB Receive Data register (USBRxData - 0xFFE0 C218)
9.6.2 USB Receive Packet Length register (USBRxPLen - 0xFFE0 C220)
9.6.3 USB Transmit Data register (USBTxData - 0xFFE0 C21C)
9.6.4 USB Transmit Packet Length register (USBTxPLen - 0xFFE0 C224)
9.6.5 USB Control register (USBCtrl - 0xFFE0 C228)
9.7 SIE command code registers
9.7.1 USB Command Code register (USBCmdCode - 0xFFE0 C210)
9.7.2 USB Command Data register (USBCmdData - 0xFFE0 C214)
9.8 DMA registers
9.8.1 USB DMA Request Status register (USBDMARSt - 0xFFE0 C250)
9.8.2 USB DMA Request Clear register (USBDMARClr - 0xFFE0 C254)
9.8.3 USB DMA Request Set register (USBDMARSet - 0xFFE0 C258)
9.8.4 USB UDCA Head register (USBUDCAH - 0xFFE0 C280)
9.8.5 USB EP DMA Status register (USBEpDMASt - 0xFFE0 C284)
9.8.6 USB EP DMA Enable register (USBEpDMAEn - 0xFFE0 C288)
9.8.7 USB EP DMA Disable register (USBEpDMADis - 0xFFE0 C28C)
9.8.8 USB DMA Interrupt Status register (USBDMAIntSt - 0xFFE0 C290)
9.8.9 USB DMA Interrupt Enable register (USBDMAIntEn - 0xFFE0 C294)
9.8.10 USB End of Transfer Interrupt Status register (USBEoTIntSt - 0xFFE0 C2A0)
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9.8.18 USB System Error Interrupt Set register (USBSysErrIntSet - 0xFFE0 C2C0)
10. Interrupt handling
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For simplicity, USBDevIntEn and USBDMAIntEn are not shown.
Fig 47. Interrupt event handling
11. Serial interface engine command description
11.1 Set Address (Command: 0xD0, Data: write 1 byte)
11.2 Configure Device (Command: 0xD8, Data: write 1 byte)
11.3 Set Mode (Command: 0xF3, Data: write 1 byte)
11.4 Read Current Frame Number (Command: 0xF5, Data: read 1 or 2 bytes)
11.5 Read Test Register (Command: 0xFD, Data: read 2 bytes)
11.6 Set Device Status (Command: 0xFE, Data: write 1 byte)
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11.9 Read Error Status (Command: 0xFB, Data: read 1 byte)
11.10 Select Endpoint (Command: 0x00 - 0x1F, Data: read 1 byte (optional))
11.11 Select Endpoint/Clear Interrupt (Command: 0x40 - 0x5F, Data: read 1 byte)
11.12 Set Endpoint Status (Command: 0x40 - 0x55, Data: write 1 byte (optional))
11.13 Clear Buffer (Command: 0xF2, Data: read 1 byte (optional))
11.14 Validate Buffer (Command: 0xFA, Data: none)
12. USB device controller initialization
13. Slave mode operation
13.1 Interrupt generation
13.2 Data transfer for OUT endpoints
13.3 Data transfer for IN endpoints
14. DMA operation
14.1 Transfer terminology
14.2 USB device communication area
14.3 Triggering the DMA engine
14.4 The DMA descriptor
14.4.1 Next_DD_pointer
14.4.2 DMA_mode
14.4.3 Next_DD_valid
14.4.4 Isochronous_endpoint
14.4.5 Max_packet_size
14.4.10 Packet_valid
14.4.11 LS_byte_extracted
14.4.12 MS_byte_extracted
14.4.13 Present_DMA_count
14.5 Non-isochronous endpoint operation
14.5.1 Setting up DMA transfers
14.5.2 Finding DMA Descriptor
14.5.3 Transferring the data
14.5.4 Optimizing descriptor fetch
14.5.5 Ending the packet transfer
14.5.6 No_Packet DD
14.6 Isochronous endpoint operation
14.6.1 Setting up DMA transfers
14.6.2 Finding the DMA Descriptor
14.6.3 Transferring the Data
14.6.4 DMA descriptor completion
14.6.5 Isochronous OUT Endpoint Operation Example
14.7 Auto Length Transfer Extraction (ATLE) mode operation
Fig 49. Isochronous OUT endpoint operation example
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14.7.1 Setting up the DMA transfer
14.7.2 Finding the DMA Descriptor
14.7.3 Transferring the Data
14.7.4 Ending the packet transfer
15. Double buffered endpoint operation
15.1 Bulk endpoints
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15.2 Isochronous endpoints
2.1 Features
Chapter 14: LPC24XX USB Host controller
2.2 Architecture
The architecture of the USB host controller is shown below in Figure 1451.
3. Interfaces
3.1 Pin description
Fig 51. USB Host controller block diagram
Table 359. USB OTG port pins Pin name Direction Description Pin category
VBUS IV
3.2 Software interface
3.2.1 Register map
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3.2.2 USB Host Register Definitions
Refer to the OHCI specification document for register definitions.
4. Architecture
Chapter 15: LPC24XX USB OTG controller
5. Modes of operation
6. Pin configuration
6.1 Connecting port U1 to an external OTG transceiver
Fig 53. USB OTG port configuration: port U1 OTG Dual-Role device, port U2 host
ISP1301
Fig 54. USB OTG port configuration: VP_VM mode
LPC24XX ISP1301
6.2 Connecting USB as a two-port host
Fig 55. USB OTG port configuration: port U2 host, port U1 host
6.3 Connecting USB as one port host and one port device
Fig 56. USB OTG port configuration: port U1 host, port U2 device
USBIntSt 0xE01F C1C0 R/W USB Interrupt Status
OTG regi sters
OTGIntSt 0xFFE0 C100 RO OTG Interrupt Status OTGIntEn 0xFFE0C104 R/W OTG Interrupt Enable
7.1 USB Interrupt Status Register (USBIntSt - 0xE01F C1C0)
7.2 OTG Interrupt Status Register (OTGIntSt - 0xE01F C100)
7.3 OTG Interrupt Enable Register (OTGIntEn - 0xFFE0 C104)
7.4 OTG Interrupt Set Register (OTGIntSet - 0xFFE0 C20C)
7.5 OTG Interrupt Clear Register (OTGIntClr - 0xFFE0 C10C)
7.6 OTG Status and Control Register (OTGStCtrl - 0xFFE0 C110)
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7.7 OTG Timer Register (OTGTmr - 0xFFE0 C114)
7.8 OTG Clock Control Register (OTGClkCtrl - 0xFFE0 CFF4)
7.9 OTG Clock Status Register (OTGClkSt - 0xFFE0 CFF8)
7.10 I2C Receive Register (I2C_RX - 0xFFE0 C300)
7.11 I2C Transmit Register (I2C_TX - 0xFFE0 C300)
7.12 I2C Status Register (I2C_STS - 0xFFE0 C304)
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7.13 I2C Control Register (I2C_CTL - 0xFFE0 C308)
7.14 I2C Clock High Register (I2C_CLKHI - 0xFFE0 C30C)
7.15 I2C Clock Low Register (I2C_CLKLO - 0xFFE0 C310)
7.16 Interrupt handling
8. HNP support
8.1 B-device: peripheral to host switching
Fig 60. Hardware support for B-device switching from peripheral state to host state
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8.2 A-device: host to peripheral HNP switching
Fig 62. Hardware support for A-device switching from host state to peripheral state
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9. Clocking and power management
9.1 Device clock request signals
Fig 64. Clocking and power control
9.1.1 Host clock request signals
9.2 Power-down mode support
10. USB OTG controller initialization
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Chapter 16: LPC24XX Universal Asynchronous Receiver/Transmitter (UART) 0/2/3
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The UnIER is used to enable the three UARTn interrupt sources.
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4.7 UARTn Line Control Register (U0LCR - 0xE000 C00C, U2LCR - 0xE007 800C, U3LCR - 0xE007 C00C)
The UnLSR is a read-only register that provides status information on the UARTn TX and RX blocks.
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4.9 UARTn Scratch Pad Register (U0SCR - 0xE000 C01C, U2SCR - 0xE007 801C U3SCR - 0xE007 C01C)
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4.11 IrDA Control Register for UART3 Only (U3ICR - 0xE007 C024)
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4.12.1 Baudrate calculation
Fig 66. Algorithm for setting UART dividers
4.13 UARTn Transmit Enable Register (U0TER - 0xE000 C030, U2TER - 0xE007 8030, U3TER - 0xE007 C030)
5. Architecture
Fig 67. UART0, 2 and 3 block diagram
Chapter 17: LPC24XX Universal Asynchronous Receiver/Transmitter (UART) 1
4. Register description
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4.1 UART1 Receiver Buffer Register (U1RBR - 0xE001 0000, when DLAB = 0 Read Only)
4.2 UART1 Transmitter Holding Register (U1THR - 0xE001 0000 when DLAB = 0, Write Only)
(3)
4.4 UART1 Interrupt Enable Register (U1IER - 0xE001 0004, when DLAB = 0)
=
--------------------------------------------------------------------------------
The U1IER is used to enable the four UART1 interrupt sources.
UART1baudrate pclk 16 256 U1 DLMU1DLL+()
4.5 UART1 Interrupt Identification Register (U1IIR - 0xE001 0008, Read Only)
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4.6 UART1 FIFO Control Register (U1FCR - 0xE001 0008, Write Only)
The U1FCR controls the operation of the UART1 RX and TX FIFOs.
4.7 UART1 Line Control Register (U1LCR - 0xE001 000C)
The U1LCR determines the format of the data character that is to be transmitted or received.
4.8 UART1 Modem Control Register (U1MCR - 0xE001 0010)
The U1MCR enables the modem loopback mode and controls the modem output signals.
4.9 Auto-flow control
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4.10 UART1 Line Status Register (U1LSR - 0xE001 0014, Read Only)
The U1LSR is a read-only register that provides status information on the UART1 TX and RX blocks.
4.11 UART1 Modem Status Register (U1MSR - 0xE001 0018)
4.12 UART1 Scratch Pad Register (U1SCR - 0xE001 001C)
4.13 UART1 Auto-baud Control Register (U1ACR - 0xE001 0020)
4.14 Auto-baud
4.15 Auto-baud modes
4.16 UART1 Fractional Divider Register (U1FDR - 0xE001 0028)
4.16.1 Baudrate calculation
Fig 71. Algorithm for setting UART dividers
4.17 UART1 Transmit Enable Register (U1TER - 0xE001 0030)
5. Architecture
Fig 72. UART1 block diagram
3. CAN controllers
Chapter 18: LPC24XX CAN controllers CAN1/2
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6. CAN controller architecture
6.1 APB Interface Block (AIB)
6.2 Interface Management Logic (IML)
6.3 Transmit Buffers (TXB)
6.4 Receive Buffer (RXB)
6.5 Error Management Logic (EML)
6.6 Bit Timing Logic (BTL)
6.7 Bit Stream Processor (BSP)
6.8 CAN controller self-tests
Page
7. Memory map of the CAN block
The CAN Controllers and Acceptance Filter occupy a number of APB slots, as follows:
8. Register description
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8.1 Mode Register (CAN1MOD - 0xE004 4000, CAN2MOD - 0xE004 8000)
8.2 Command Register (CAN1CMR - 0xE004 x004, CAN2CMR - 0xE004 8004)
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8.3 Global Status Register (CAN1GSR - 0xE004 x008, CAN2GSR - 0xE004 8008)
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8.4 Interrupt and Capture Register (CAN1ICR - 0xE004 400C, CAN2ICR - 0xE004 800C)
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8.5 Interrupt Enable Register (CAN1IER - 0xE004 4010, CAN2IER - 0xE004 8010)
8.6 Bus Timing Register (CAN1BTR - 0xE004 4014, CAN2BTR - 0xE004 8014)
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8.7 Error Warning Limit Register (CAN1EWL - 0xE004 4018, CAN2EWL - 0xE004 8018)
8.8 Status Register (CAN1SR - 0xE004 401C, CAN2SR - 0xE004 801C)
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8.9 Receive Frame Status Register (CAN1RFS - 0xE004 4020, CAN2RFS - 0xE004 8020)
8.9.1 ID index field
8.10 Receive Identifier Register (CAN1RID - 0xE004 4024, CAN2RID - 0xE004 8024)
8.11 Receive Data Register A (CAN1RDA - 0xE004 4028, CAN2RDA - 0xE004 8028)
8.12 Receive Data Register B (CAN1RDB - 0xE004 402C, CAN2RDB - 0xE004 802C)
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9. CAN controller operation
9.1 Error handling
9.2 Sleep mode
9.3 Interrupts
9.4 Transmit priority
10. Centralized CAN registers
10.1 Central Transmit Status Register (CANTxSR - 0xE004 0000)
10.2 Central Receive Status Register (CANRxSR - 0xE004 0004)
10.3 Central Miscellaneous Status Register (CANMSR - 0xE004 0008)
11. Global acceptance filter
12. Acceptance filter modes
12.1 Acceptance filter Off mode
12.2 Acceptance filter Bypass mode
12.3 Acceptance filter Operating mode
13. Sections of the ID look-up table RAM
14. ID look-up table RAM
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15. Acceptance filter registers
15.1 Acceptance Filter Mode Register (AFMR - 0xE003 C000)
15.2 Section configuration registers
15.3 Standard Frame Individual Start Address Register (SFF_sa - 0xE003 C004)
15.4 Standard Frame Group Start Address Register (SFF_GRP_sa - 0xE003 C008)
15.5 Extended Frame Start Address Register (EFF_sa - 0xE003 C00C)
15.6 Extended Frame Group Start Address Register (EFF_GRP_sa - 0xE003 C010)
15.7 End of AF Tables Register (ENDofTable - 0xE003 C014)
15.8 Status registers
15.9 LUT Error Address Register (LUTerrAd - 0xE003 C018)
15.10 LUT Error Register (LUTerr - 0xE003 C01C)
15.11 Global FullCANInterrupt Enable register (FCANIE - 0xE003 C020)
15.12 FullCAN Interrupt and Capture registers (FCANIC0 - 0xE003 C024 and FCANIC1 - 0xE003 C028)
For detailed description on these two registers, see Section 1817.2 FullCAN interrupts.
16. Configuration and search algorithm
16.1 Acceptance filter search algorithm
17. FullCAN mode
Fig 81. ID Look-up table example explaining the search algorithm
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17.1 FullCAN message layout
Fig 82. Semaphore procedure for reading an auto-stored message
17.2 FullCAN interrupts
17.2.1 FullCAN message interrupt enable bit
17.2.2 Message lost bit and CAN channel number
Fig 83. FullCAN section example of the ID look-up table
Fig 84. FullCAN message object layout
CAN
17.2.3 Setting the interrupt pending bits (IntPnd 63 to 0)
17.3 Set and clear mechanism of the FullCAN interrupt
17.3.1 Scenario 1: Normal case, no message lost
17.3.2 Scenario 2: Message lost
Fig 86. Message lost
Fig 85. Normal case, no messages lost
17.3.3 Scenario 3: Message gets overwritten indicated by Semaphore bits
17.3.4 Scenario 3.1: Message gets overwritten indicated by Semaphore bits and Message Lost
Fig 87. Message gets overwritten
17.3.5 Scenario 3.2: Message gets overwritten indicated by Message Lost
This scenario is a sub-case to Scenario 3 in which the lost message is indicated by Message Lost.
Fig 88. Message overwritten indicated by semaphore bits and message lost
17.3.6 Scenario 4: Clearing Message Lost bit
Fig 89. Message overwritten indicated by message lost
18. Examples of acceptance filter tables and ID index values
18.1 Example 1: only one section is used
18.2 Example 2: all sections are used
18.3 Example 3: more than one but not all sections are used
Fig 90. Clearing message lost
18.4 Configuration example 4
18.5 Configuration example 5
18.6 Configuration example 6
Fig 91. Detailed example of acceptance filter tables and ID index values
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18.7 Configuration example 7
Fig 92. ID Look-up table configuration example (no FullCAN)
Table 458. Use d ID -Look-up Table sections ID-Look-up Table Section Stat us
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18.8 Look-up table programming guidelines
Fig 93. ID Look-up table configuration example (FullCAN activated and enabled)
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3. SPI overview
4. SPI data transfers
Chapter 19: LPC24XX SPI
5. SPI peripheral details
5.1 General information
5.2 Master operation
5.3 Slave operation
5.4 Exception conditions
6. Pin description
7.1 SPI Control Register (S0SPCR - 0xE002 0000)
The S0SPCR register controls the operation of the SPI0 as per the configuration bits setting.
7.2 SPI Status Register (S0SPSR - 0xE002 0004)
The S0SPSR register controls the operation of the SPI0 as per the configuration bits setting.
7.3 SPI Data Register (S0SPDR - 0xE002 0008)
7.4 SPI Clock Counter Register (S0SPCCR - 0xE002 000C)
7.5 SPI Test Control Register (SPTCR - 0xE002 0010)
7.6 SPI Test Status Register (SPTSR - 0xE002 0014)
7.7 SPI Interrupt Register (S0SPINT - 0xE002 001C)
8. Architecture
Fig 95. SPI block diagram
Chapter 20: LPC24XX SSP interface SSP0/1
4. Pin descriptions
5. Bus description
5.1 Texas Instruments synchronous serial frame format
5.2 SPI frame format
5.2.1 Clock Polarity (CPOL) and Phase (CPHA) control
5.2.2 SPI format with CPOL=0,CPHA=0
5.2.3 SPI format with CPOL=0,CPHA=1
5.2.4 SPI format with CPOL = 1,CPHA = 0
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5.2.5 SPI format with CPOL = 1,CPHA = 1
5.3 Semiconductor Microwire frame format
5.3.1 Setup and hold time requirements on CS with respect to SK in Microwire mode
6.1 SSPn Control Register 0 (SSP0CR0 - 0xE006 8000, SSP1CR0 - 0xE003 0000)
This register controls the basic operation of the SSP controller.
6.2 SSPn Control Register 1 (SSP0CR1 - 0xE006 8004, SSP1CR1 - 0xE003 0004)
This register controls certain aspects of the operation of the SSP controller.
6.3 SSPn Data Register (SSP0DR - 0xE006 8008, SSP1DR - 0xE003 0008)
Software can write data to be transmitted to this register, and read data that has been received.
6.4 SSPn Status Register (SSP0SR - 0xE006 800C, SSP1SR - 0xE003 000C)
6.5 SSPn Clock Prescale Register (SSP0CPSR - 0xE006 8010, SSP1CPSR - 0xE003 0010)
6.6 SSPn Interrupt Mask Set/Clear Register (SSP0IMSC - 0xE006 8014, SSP1IMSC - 0xE003 0014)
6.7 SSPn Raw Interrupt Status Register (SSP0RIS - 0xE006 8018, SSP1RIS - 0xE003 0018)
6.8 SSPn Masked Interrupt Status Register (SSP0MIS - 0xE006 801C, SSP1MIS - 0xE003 001C)
6.9 SSPn Interrupt Clear Register (SSP0ICR - 0xE006 8020, SSP1ICR - 0xE003 0020)
6.10 SSPn DMA Control Register (SSP0DMACR - 0xE006 8024, SSP1DMACR - 0xE003 0024)
3. Features of the MCI
4. SD/MMC card interface pin description
Chapter 21: LPC24XX SD/MMC card interface
5. Functional overview
5.2.1 Secure digital memory card bus signals
5.3 MCI adapter
5.3.1 Adapter register block
5.3.2 Control unit
5.3.3 Command path
5.3.4 Command path state machine
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5.3.5 Command format
5.3.6 Data path
5.3.7 Data path state machine
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5.3.9 Bus mode
5.3.10 CRC Token status
5.3.11 Status flags
5.3.12 CRC generator
5.3.13 Data FIFO
5.3.14 Transmit FIFO
5.3.15 Receive FIFO
5.3.16 APB interfaces
5.3.17 Interrupt logic
6.1 Power Control Register (MCI Power - 0xE008 C000)
6.2 Clock Control Register (MCIClock - 0xE008 C004)
6.3 Argument Register (MCIArgument - 0xE008 C008)
6.4 Command Register (MCICommand - 0xE008 C00C)
6.5 Command Response Register (MCIRespCommand - 0xE008 C010)
6.6 Response Registers (MCIResponse0-3 - 0xE008 C014, E008 C018, E008 C01C and E008 C020)
6.7 Data Timer Register (MCIDataTimer - 0xE008 C024)
6.8 Data Length Register (MCIDataLength - 0xE008 C028)
6.9 Data Control Register (MCIDataCtrl - 0xE008 C02C)
6.10 Data Counter Register (MCIDataCnt - 0xE008 C030)
6.11 Status Register (MCIStatus - 0xE008 C034)
Chapter 21: LPC24XX SD/MMC card interface
6.12 Clear Register (MCIClear - 0xE008 C038)
6.13 Interrupt Mask Registers (MCIMask0 - 0xE008 C03C)
6.14 FIFO Counter Register (MCIFifoCnt - 0xE008 C048)
6.15 Data FIFO Register (MCIFIFO - 0xE008 C080 to 0xE008 C0BC)
Chapter 22: LPC24XX I2C interfaces I2C0/1/2
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6. I2C operating modes
6.1 Master Transmitter mode
6.2 Master Receiver mode
6.3 Slave Receiver mode
6.4 Slave Transmitter mode
7. I2C implementation and operation
7.1 Input filters and output stages
Fig 117. I2C Bus serial interface block diagram
7.2 Address Register I2ADDR
7.3 Comparator
7.4 Shift register I2DAT
7.5 Arbitration and synchronization logic
7.6 Serial clock generator
7.7 Timing and control
7.8 Control register I2CONSET and I2CONCLR
7.9 Status decoder and status register
8. Register description
8.1 I2C Control Set Register (I2C[0/1/2]CONSET: 0xE001C000, 0xE005 C000, 0xE008 0000)
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8.2 I2C Control Clear Register (I2C[0/1/2]CONCLR: 0xE001 C018, 0xE005 C018, 0xE008 0018)
8.3 I2C Status Register (I2C[0/1/2]STAT - 0xE001 C004, 0xE005 C004, 0xE008 0004)
8.4 I2C Data Register (I2C[0/1/2]DAT - 0xE001 C008, 0xE005 C008, 0xE008 0008)
8.5 I2C Slave Address Register (I2C[0/1/2]ADR - 0xE001 C00C, 0xE005 C00C, 0xE008 000C)
8.6 I2C SCL High Duty Cycle Register (I2C[0/1/2]SCLH - 0xE001 C010, 0xE005 C010, 0xE008 0010)
8.7 I2C SCL Low Duty Cycle Register (I2C[0/1/2]SCLL - 0xE001 C014, 0xE005 C014, 0xE008 0014)
8.8 Selecting the appropriate I2C data rate and duty cycle
9. Details of I2C operating modes
9.1 Master Transmitter mode
9.2 Master Receiver mode
9.3 Slave Receiver mode
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Fig 120. Format and States in the Master Transmitter mode
Fig 121. Format and States in the Master Receiver mode
Fig 122. Format and States in the Slave Receiver mode
9.4 Slave Transmitter mode
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9.5 Miscellaneous states
9.6 Some special cases
9.7 Simultaneous repeated START conditions from two masters
9.8 Data transfer after loss of arbitration
9.9 Forced access to the I2C bus
9.10 I2C Bus obstructed by a Low level on SCL or SDA
9.11 Bus error
9.12 I2C State service routines
9.12.1 Initialization
9.12.2 I2C interrupt service
10. Software example
10.1 Initialization routine
10.2 Start master transmit function
10.3 Start master receive function
10.4 I2C interrupt routine
10.5 Non mode specific states
10.5.1 State : 0x00
10.6 Master states
10.6.1 State : 0x08
10.7 Master Transmitter states
10.7.1 State : 0x18
10.7.2 State : 0x20
10.7.3 State : 0x28
10.7.4 State : 0x30
10.8 Master Receive states
10.8.1 State : 0x40
10.8.2 State : 0x48
10.8.3 State : 0x50
10.8.4 State : 0x58
10.9 Slave Receiver states
10.9.1 State : 0x60
10.9.2 State : 0x68
10.9.3 State : 0x70
10.9.4 State : 0x78
10.9.5 State : 0x80
10.9.6 State : 0x88
10.9.7 State : 0x90
10.9.8 State : 0x98
10.9.9 State : 0xA0
10.10 Slave Transmitter States
10.10.1 State : 0xA8
10.10.2 State : 0xB0
10.10.3 State : 0xB8
10.10.4 State : 0xC0
10.10.5 State : 0xC8
Chapter 23: LPC24XX I2S interface
4. Pin descriptions
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5.1 Digital Audio Output Register (I2SDAO - 0xE008 8000)
5.2 Digital Audio Input Register (I2SDAI - 0xE008 8004)
5.3 Transmit FIFO Register (I2STXFIFO - 0xE008 8008)
5.4 Receive FIFO Register (I2SRXFIFO - 0xE008 800C)
5.5 Status Feedback Register (I2SSTATE - 0xE0088010)
5.6 DMA Configuration Register 1 (I2SDMA1 - 0xE008 8014)
5.7 DMA Configuration Register 2 (I2SDMA2 - 0xE008 8018)
5.8 Interrupt Request Control Register (I2SIRQ - 0xE008 801C)
5.9 Transmit Clock Rate Register (I2STXRATE - 0xE008 8020)
5.10 Receive Clock Rate Register (I2SRXRATE - 0xE008 8024)
6. I2S transmit and receive interfaces
7. FIFO controller
System signaling occurs when a level detection is true and enabled.
Fig 128. FIFO contents for various I2S modes
Chapter 24: LPC24XX Timer0/1/2/3
5.1 Multiple CAP and MAT pins
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6.1 Interrupt Register (T[0/1/2/3]IR - 0xE000 4000, 0xE000 8000, 0xE007 0000, 0xE007 4000)
The Timer Control Register (TCR) is used to control the operation of the Timer/Counter.
6.2 Timer Control Register (T[0/1/2/3]CR - 0xE000 4004, 0xE000 8004, 0xE007 0004, 0xE007 4004)
6.3 Count Control Register (T[0/1/2/3]CTCR - 0xE000 4070, 0xE000 8070, 0xE007 0070, 0xE007 4070)
6.4 Timer Counter registers (T0TC - T3TC, 0xE000 4008, 0xE000 8008, 0xE007 0008, 0xE007 4008)
6.5 Prescale register (T0PR - T3PR, 0xE000 400C, 0xE000 800C, 0xE007 000C, 0xE007 400C)
6.6 Prescale Counter register (T0PC - T3PC, 0xE000 4010, 0xE000 8010, 0xE007 0010, 0xE007 4010)
6.7 Match Registers (MR0 - MR3)
6.8 Match Control Register (T[0/1/2/3]MCR - 0xE000 4014, 0xE000 8014, 0xE007 0014, 0xE007 4014)
6.9 Capture Registers (CR0 - CR3)
6.10 Capture Control Register (T[0/1/2/3]CCR - 0xE000 4028, 0xE000 8028, 0xE007 0028, 0xE007 4028)
6.11 External Match Register (T[0/1/2/3]EMR - 0xE000 403C, 0xE000 803C, 0xE007 003C, 0xE007 403C)
7. Example timer operation
8. Architecture
Fig 131. Timer block diagram
Chapter 25: LPC24XX Pulse Width Modulator PWM0/PWM1
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Fig 132. PWM block diagram
3.1 Rules for single edge controlled PWM outputs
3.2 Rules for double edge controlled PWM outputs
3.3 Summary of differences from the standard timer block
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Table25555 gives a brief summary of each of PWM related pins.
5. PWM base addresses
The PWM0 and PWM1 function adds new registers and registers bits as shown in Table25557 below.
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6.1 PWM Interrupt Register (PWM0IR - 0xE001 4000 and PWM1IR 0xE001 8000)
6.2 PWM Timer Control Register (PWM0TCR - 0xE001 4004 and PWM1TCR 0xE001 8004)
6.3 PWM Count Control Register (PWM0CTCR - 0xE001 4070 and PWM1CTCR 0xE001 8070)
6.4 PWM Match Control Register (PWM0MCR - 0xE001 4014 and PWM1MCR 0xE001 8014)
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6.5 PWM Capture Control Register (PWM0CCR - 0xE001 4028 and PWM1CCR 0xE001 8028)
6.6 PWM Control Registers (PWM0PCR - 0xE001 404C and PWM1PCR 0xE001 804C)
6.7 PWM Latch Enable Register (PWM0LER - 0xE001 4050 and PWM1LER 0xE001 8050)
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Chapter 26: LPC24XX Real-Time Clock (RTC) and battery RAM
4. Architecture
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6.1 RTC interrupts
6.2 Miscellaneous register group
6.2.1 Interrupt Location Register (ILR - 0xE002 4000)
6.2.2 Clock Tick Counter Register (CTCR - 0xE002 4004)
6.2.3 Clock Control Register (CCR - 0xE002 4008)
6.2.4 Counter Increment Interrupt Register (CIIR - 0xE002 400C)
6.2.5 Counter Increment Select Mask Register (CISS - 0xE002 4040)
6.2.6 Alarm Mask Register (AMR - 0xE002 4010)
6.3 Consolidated time registers
6.3.1 Consolidated Time Register 0 (CTIME0 - 0xE002 4014)
6.3.2 Consolidated Time Register 1 (CTIME1 - 0xE002 4018)
6.3.3 Consolidated Time Register 2 (CTIME2 - 0xE002 401C)
6.4 Time Counter Group
6.4.1 Leap year calculation
7. Alarm register group
8. Alarm output
9. RTC usage notes
10. RTC clock generation
10.1 Reference Clock Divider (Prescaler)
10.2 Prescaler Integer Register (PREINT - 0xE002 4080)
10.3 Prescaler Fraction Register (PREFRAC - 0xE002 4084)
10.4 Example of Prescaler Usage
10.5 Prescaler operation
11. Battery RAM
12. RTC external 32 kHz oscillator component selection
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Chapter 27: LPC24XX WatchDog Timer (WDT)
4. Register description
4.1 Watchdog Mode Register (WDMOD - 0xE000 0000)
4.2 Watchdog Timer Constant Register (WDTC - 0xE000 0004)
4.3 Watchdog Feed Register (WDFEED - 0xE000 0008)
4.4 Watchdog Timer Value Register (WDTV - 0xE000 000C)
4.5 Watchdog Timer Clock Source Selection Register (WDCLKSEL - 0xE000 0010)
Chapter 27: LPC24XX WatchDog Timer (WDT)
5. Block diagram
Fig 137. Watchdog block diagram
Chapter 28: LPC24XX Analog-to Digital Converter (ADC)
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5.1 A/D Control Register (AD0CR - 0xE003 4000)
5.2 A/D Global Data Register (AD0GDR - 0xE003 4004)
5.3 A/D Status Register (AD0STAT - 0xE0034030)
5.4 A/D Interrupt Enable Register (AD0INTEN - 0xE003 400C)
5.5 A/D Data Registers (AD0DR0 to AD0DR7 - 0xE003 4010 to 0xE003 402C)
6. Operation
6.1 Hardware-triggered conversion
6.2 Interrupts
6.3 Accuracy vs. digital receiver
4. Register description (DACR - 0xE006 C000)
Chapter 29: LPC24XX Digital-to Analog Converter (DAC)
5. Operation
2. Flash boot loader
5. Description
Chapter 30: LPC24XX Flash memory programming firmware
5.1 Memory map after any reset
5.1.1 Criterion for Valid User Code
5.2 Communication protocol
5.2.1 ISP command format
5.2.2 ISP response format
5.2.3 ISP data format
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6. Boot process flowchart
Fig 139. Boot process flowchart
7. Sector numbers
8. Code Read Protection (CRP)
9. ISP commands
9.1 Unlock <Unlock code>
9.2 Set Baud Rate <Baud Rate> <stop bit>
9.3 Echo <setting>
9.4 Write to RAM <start address> <number of bytes>
9.5 Read Memory <address> <no. of bytes>
9.6 Prepare sector(s) for write operation <start sector number> <end sector number>
This command makes Flash write/erase operation a two step process.
9.7 Copy RAM to Flash <Flash address> <RAM address> <no of bytes>
9.8 Go <address> <mode>
9.9 Erase sector(s) <start sector number> <end sector number>
9.10 Blank check sector(s) <sector number> <end sector number>
9.11 Read Part Identification number
9.12 Read Boot code version number
9.13 Compare <address1> <address2> <no of bytes>
9.14 ISP Return Codes
10. IAP commands
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10.1 Prepare sector(s) for write operation
This command makes Flash write/erase operation a two step process.
Table 621. IAP Command Summary IAP Command Command Code Described in
Fig 140. IAP parameter passing
10.2 Copy RAM to Flash
10.3 Erase Sector(s)
10.4 Blank check sector(s)
10.5 Read Part Identification number
10.6 Read Boot code version number
10.7 Compare <address1> <address2> <no of bytes>
10.8 Reinvoke ISP
10.9 IAP Status Codes
11. JTAG Flash programming interface
Chapter 31: LPC24XX On-chip bootloader for flashless parts
4.1 Memory map after any reset
4.2 Communication protocol
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4.2.9 RAM used by IAP command handler
4.2.10 RAM used by RealMonitor
5. Boot process flowchart
(1) For details on handling the crystal frequency, see Section 317.4 Reinvoke ISP on page 709
Fig 142. Boot process flowchart
6. ISP commands
6.1 Unlock <Unlock code>
6.2 Set Baud Rate <Baud Rate> <stop bit>
6.3 Echo <setting>
6.4 Write to RAM <start address> <number of bytes>
6.5 Read Memory <address> <no. of bytes>
6.6 Go <address> <mode>
6.7 Read Part Identification number
6.8 Read Boot code version number
6.9 Compare <address1> <address2> <no of bytes>
6.10 ISP Return Codes
7. IAP commands
Page
7.1 Read Part Identification number
7.2 Read Boot code version number
7.3 Compare <address1> <address2> <no of bytes>
7.4 Reinvoke ISP
7.5 IAP Status Codes
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3. Features of the GPDMA
Chapter 32: LPC24XX General Purpose DMA (GPDMA) controller
4. Functional overview
4.2.1 AHB Slave Interface
4.2.2 Control Logic and Register Bank
4.2.3 DMA Request and Response Interface
4.2.4 Channel Logic and Channel Register Bank
Table32651 shows endian behavior for different source and destination combinations.
4.2.9 Error conditions
4.2.10 Channel hardware
4.2.11 DMA request priority
4.2.12 Interrupt generation
4.2.13 The completion of the DMA transfer indication
4.3 DMA system connections
5. Programming the GPDMA
5.1 Enabling the GPDMA
5.2 Disabling the GPDMA
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5.9 Programming a DMA channel
6.1 General GPDMA registers
This section describes the registers of the GPDMA.
6.1.1 Interrupt Status Register (DMACIntStatus - 0xFFE0 4000)
6.1.2 Interrupt Terminal Count Status Register (DMACIntTCStatus - 0xFFE04004)
6.1.3 Interrupt Terminal Count Clear Register (DMACIntClear - 0xFFE0 4008)
6.1.4 Interrupt Error Status Register (DMACIntErrorStatus - 0xFFE0 400C)
6.1.5 Interrupt Error Clear Register (DMACIntErrClr - 0xFFE0 4010)
6.1.6 Raw Interrupt Terminal Count Status Register (DMACRawIntTCStatus - 0xFFE0 4014)
6.1.7 Raw Error Interrupt Status Register (DMACRawIntErrorStatus - 0xFFE0 4018)
6.1.8 Enabled Channel Register (DMACEnbldChns - 0xFFE0 401C)
6.1.9 Software Burst Request Register (DMACSoftBReq - 0xFFE0 4020)
6.1.10 Software Single Request Register (DMACSoftSReq - 0xFFE0 4024)
6.1.11 Software Last Burst Request Register (DMACSoftLBreq - 0xFFE0 4028)
6.1.12 Software Last Single Request Register (DMACSoftLSReq - 0xFFE0 402C)
6.1.13 Configuration Register (DMACConfiguration - 0xFFE0 4030)
6.1.14 Synchronization Register (DMACSync - 0xFFE0 4034)
6.2 Channel registers
6.2.3 Channel Linked List Item Registers (DMACC0LLI - 0xFFE0 4108 and DMACC1LLI - 0xFFE0 4128)
6.2.4 Channel Control Registers (DMACC0Control - 0xFFE0 410C and DMACC0Control - 0xFFE0 412C)
Table32672 shows the value of the 3 bit DBSize or SBSize fields and the corresponding burst sizes.
6.2.5 Protection and Access Information
Page
6.2.7 Lock control
6.2.8 Flow control and transfer type
7. Address generation
8. Scatter/Gather
8.1 Linked List Items
8.2 Programming the GPDMA for scatter/gather DMA
8.3 Example of scatter/gather DMA
9. Interrupt requests
9.1 Hardware interrupt sequence flow
9.2 Interrupt polling sequence flow
10. GPDMA data flow
10.1 Peripheral-to-memory, or Memory-to-peripheral DMA flow
10.2 Peripheral-to-peripheral DMA flow
10.3 Memory-to-memory DMA flow
11. Fl ow contr ol
Chapter 33: LPC24XX EmbeddedICE
Page
5. JTAG function select
7. Block diagram
Chapter 33: LPC24XX EmbeddedICE
Fig 147. EmbeddedICE debug environment block diagram
3.1 ETM configuration
Chapter 34: LPC24XX Embedded Trace Module (ETM)
Page
6. Reset state of multiplexed pins
7. Block diagram
The block diagram of the ETM debug environment is shown below in Figure 34148.
5
Fig 148. ETM debug environment block diagram
10
Chapter 35: LPC24XX RealMonitor
3.1 RealMonitor components
3.1.1 RMHost
3.1.2 RMTarget
3.2 How RealMonitor works
4. How to enable RealMonitor
4.1 Adding stacks
4.2 IRQ mode
4.3 Undef mode
4.4 SVC mode
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4.10 RMTarget initialization
4.11 Code example
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5. RealMonitor build options
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1. Abbreviations
Chapter 36: LPC24XX Supplementary information
2. Legal information
2.1 Definitions
2.2 Disclaimers
2.3 Trademarks
3. Tables
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4. Figures
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5. Contents
Chapter 1: LPC24XX Introductory information
Chapter 2: LPC24XX Memory mapping
Chapter 3: LPC24XX System control
Chapter 4: LPC24XX Clocking and power control
Chapter 5: LPC24XX External Memory Controller (EMC)
Chapter 6: LPC24XX Memory Accelerator Module (MAM)
Chapter 7: LPC24XX Vectored Interrupt Controller (VIC)
Chapter 8: LPC24XX Pin configuration
Chapter 9: LPC24XX Pin connect
Chapter 10: LPC24XX General Purpose Input/Output (GPIO)
Chapter 11: LPC24XX Ethernet
Chapter 12: LPC24XX LCD controller
Chapter 13: LPC24XX USB device controller
Page
Chapter 14: LPC24XX USB Host controller
Chapter 15: LPC24XX USB OTG controller
Chapter 16: LPC24XX Universal Asynchronous Receiver/Transmitter (UART) 0/2/3
Chapter 17: LPC24XX Universal Asynchronous Receiver/Transmitter (UART) 1
Chapter 18: LPC24XX CAN controllers CAN1/2
Chapter 19: LPC24XX SPI
Chapter 20: LPC24XX SSP interface SSP0/1
Chapter 21: LPC24XX SD/MMC card interface
Chapter 22: LPC24XX I2C interfaces I2C0/1/2
Chapter 23: LPC24XX I2S interface
Chapter 24: LPC24XX Timer0/1/2/3
Chapter 25: LPC24XX Pulse Width Modulator PWM0/PWM1
Chapter 26: LPC24XX Real-Time Clock (RTC) and battery RAM
Chapter 27: LPC24XX WatchDog Timer (WDT)
Chapter 28: LPC24XX Analog-to Digital Converter (ADC)
Chapter 29: LPC24XX Digital-to Analog Converter (DAC)
Chapter 30: LPC24XX Flash memory programming firmware
Chapter 31: LPC24XX On-chip bootloader for flashless parts
Chapter 32: LPC24XX General Purpose DMA (GPDMA) controller
Chapter 33: LPC24XX EmbeddedICE
Chapter 34: LPC24XX Embedded Trace Module (ETM)
Chapter 35: LPC24XX RealMonitor
Chapter 36: LPC24XX Supplementary information
