NXP Semiconductors UM10237

User manual Rev. 02 — 19 December 2008 771 o f 792

Chapter 36: LPC24XX Supplementary information

Table 573.Alarm Mask Register (AMR - address

0xE002 4010) bit description . . . . . . . . . . . . .653

Table 574.Consolidated Time register 0 (CTIME0 - address

0xE002 4014) bit description . . . . . . . . . . . . .654

Table 575.Consolidated Time register 1 (CTIME1 - address

0xE002 4018) bit description . . . . . . . . . . . . .654

Table 576.Consolidated Time register 2 (CTIME2 - address

0xE002 401C) bit description. . . . . . . . . . . . .655

Table 577.Time Counter relationships and values). . . . . 655

Table 578.Time Counter registers. . . . . . . . . . . . . . . . . .655

Table 579.Alarm registers. . . . . . . . . . . . . . . . . . . . . . . .656

Table 580.Reference Clock Divider registers . . . . . . . . . 657

Table 581:Prescaler Integer register (PREINT - address

0xE002 4080) bit description . . . . . . . . . . . . .658

Table 582:Prescaler Integer register (PREFRAC - address

0xE002 4084) bit description . . . . . . . . . . . . .658

Table 583.Prescaler cases where the Integer Counter reload

value is incremented. . . . . . . . . . . . . . . . . . . .660

Table 584.Recommended values for the RTC external

32 kHz oscillator CX1/X2 components . . . . . . .661

Table 585.Summary of Watchdog registers . . . . . . . . . . 663

Table 586.Watchdog operating modes selection. . . . . . .664

Table 587:Watchdog Mode register (WDMOD - address

0xE000 0000) bit description . . . . . . . . . . . . .664

Table 588:Watchdog Constant register (WDTC - address

0xE000 0004) bit description . . . . . . . . . . . . .664

Table 589:Watchdog Feed Register (WDFEED - address

0xE000 0008) bit description . . . . . . . . . . . . .665

Table 590:Watchdog Timer Value register (WDTV - address

0xE000 000C) bit description. . . . . . . . . . . . .665

Table 591:Watchdog Timer Clock Source Selection register

(WDCLKSEL - address 0xE000 0010) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . .665

Table 592.ADC pin description . . . . . . . . . . . . . . . . . . . .668

Table 593.Summary of ADC registers. . . . . . . . . . . . . . .668

Table 594:A/D Control Register (AD0CR - address

0xE003 4000) bit description . . . . . . . . . . . . .669

Table 595:A/D Global Data Register (AD0GDR - address

0xE003 4004) bit description . . . . . . . . . . . . .671

Table 596:A/D Status Register (AD0STAT - address

0xE003 4030) bit description . . . . . . . . . . . . .671

Table 597:A/D Interrupt Enable Register (AD0INTEN -

address 0xE003 400C) bit description . . . . . .672

Table 598:A/D Data Registers (AD0DR0 to AD0DR7 -

addresses 0xE003 4010 to 0xE003 402C) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . .672

Table 599.D/A Pin Description . . . . . . . . . . . . . . . . . . . .674

Table 600:D/A Converter Register (DACR - address

0xE006 C000) bit description. . . . . . . . . . . . .675

Table 601.Sectors in a LPC2400 device. . . . . . . . . . . . .681

Table 602.Code Read Protection options . . . . . . . . . . . .682

Table 603.Code Read Protection hardware/software

interaction. . . . . . . . . . . . . . . . . . . . . . . . . . . .683

Table 604.ISP command summary. . . . . . . . . . . . . . . . .683

Table 605.ISP Unlock command. . . . . . . . . . . . . . . . . . .684

Table 606.ISP Set Baud Rate command. . . . . . . . . . . . .684

Table 607.Correlation between possible ISP baudrates and

CCLK frequency (in MHz). . . . . . . . . . . . . . . .684

Table 608.ISP Echo command. . . . . . . . . . . . . . . . . . . . 685

Table 609.ISP Write to RAM command . . . . . . . . . . . . .685

Table 610.ISP Read Memory command. . . . . . . . . . . . . 686

Table 611.ISP Prepare sector(s) for write operation

command. . . . . . . . . . . . . . . . . . . . . . . . . . . . 686

Table 612.ISP Copy command. . . . . . . . . . . . . . . . . . . .687

Table 613.ISP Go command. . . . . . . . . . . . . . . . . . . . . .687

Table 614.ISP Erase sector command. . . . . . . . . . . . . . 688

Table 615.ISP Blank check sector command. . . . . . . . . 688

Table 616.ISP Read Part Identification command . . . . . 688

Table 617.LPC24xx part Identification numbers. . . . . . . 689

Table 618.ISP Read Boot Code version number

command. . . . . . . . . . . . . . . . . . . . . . . . . . . . 689

Table 619.ISP Compare command. . . . . . . . . . . . . . . . .689

Table 620.ISP Return Codes Summary . . . . . . . . . . . . .689

Table 621.IAP Command Summary. . . . . . . . . . . . . . . . 692

Table 622.IAP Prepare sector(s) for write operation

command. . . . . . . . . . . . . . . . . . . . . . . . . . . . 693

Table 623.IAP Copy RAM to Flash command . . . . . . . . 693

Table 624.IAP Erase Sector(s) command . . . . . . . . . . . 694

Table 625.IAP Blank check sector(s) command. . . . . . . 694

Table 626.IAP Read Part Identification command . . . . . 694

Table 627.IAP Read Boot Code version number command.

695

Table 628.IAP Compare command. . . . . . . . . . . . . . . . .695

Table 629.Reinvoke ISP. . . . . . . . . . . . . . . . . . . . . . . . . 695

Table 630.IAP Status Codes Summary . . . . . . . . . . . . . 696

Table 631.ISP command summary. . . . . . . . . . . . . . . . .701

Table 632.ISP Unlock command . . . . . . . . . . . . . . . . . . 701

Table 633.ISP Set Baud Rate command . . . . . . . . . . . .701

Table 634.Correlation between possible ISP baudrates and

CCLK frequency (in MHz) . . . . . . . . . . . . . . . 702

Table 635.ISP Echo command. . . . . . . . . . . . . . . . . . . . 702

Table 636.ISP Write to RAM command . . . . . . . . . . . . .703

Table 637.ISP Read Memory command. . . . . . . . . . . . . 703

Table 638.ISP Go command. . . . . . . . . . . . . . . . . . . . . .704

Table 639.ISP Read Part Identification command . . . . . 704

Table 640.LPC24xx part Identification numbers. . . . . . . 704

Table 641.ISP Read Boot Code version number

command. . . . . . . . . . . . . . . . . . . . . . . . . . . . 704

Table 642.ISP Compare command. . . . . . . . . . . . . . . . .705

Table 643.ISP Return Codes Summary . . . . . . . . . . . . .705

Table 644.IAP Command Summary. . . . . . . . . . . . . . . . 707

Table 645.IAP Read Part Identification command . . . . . 708

Table 646.IAP Read Boot Code version number

command. . . . . . . . . . . . . . . . . . . . . . . . . . . . 708

Table 647.IAP Compare command. . . . . . . . . . . . . . . . .709

Table 648.Reinvoke ISP. . . . . . . . . . . . . . . . . . . . . . . . . 709

Table 649.IAP Status Codes Summary . . . . . . . . . . . . . 709

Table 650.GPDMA accessible memory . . . . . . . . . . . . .712

Table 651.Endian behavior. . . . . . . . . . . . . . . . . . . . . . . 715

Table 652.DMA Connections . . . . . . . . . . . . . . . . . . . . .717

Table 653.Summary of GPDMA registers. . . . . . . . . . . . 720

Table 654.Interrupt Status register (DMACIntStatus -

address 0xFFE0 4000) bit description. . . . . . 722

Table 655.Interrupt Terminal Count Status register

(DMACIntTCStatus - address 0xFFE0 4004) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . .722