NXP Semiconductors UM10237 10.18 Static Memory Extended Wait register (EMCStaticExtendedWait - 0xFFE0 8080), 10.19 Dynamic Memory Configuration registers (EMCDynamicConfig0-3 - 0xFFE0 8100, 120, 140, 160)

UM10237_2 © NXP B.V. 2008. All rights reserved.
User manual Rev. 02 — 19 December 2008 87 of 792
NXP Semiconductors UM10237
Chapter 5: LPC24XX External Memory Controller (EMC)
10.18 Static Memory Extended Wait register (EMCStaticExtendedWait -
0xFFE0 8080)
ExtendedWait (EW) bit in the EMCStaticConfig register is set. It is recommended that this
register is modified during system initialization, or when there are no current or
outstanding transactions. However, if necessary, these control bits can be altered during
normal operation. This register is accessed with one wait state.
Table5–85 shows the bit assignments for the EMCStaticExtendedWait registers.
For example, for a static memory read/write transfer time of 16 µs, and a CCLK frequency
of 50 MHz, the following value must be programmed into this register: (16 x 10-6 x 50 x
106) / 16 - 1 = 49
10.19 Dynamic Memory Configuration registers (EMCDynamicConfig0-3 -
0xFFE0 8100, 120, 140, 160)
The EMCDynamicConfig0-3 registers enable you to program the configuration information
for the relevant dynamic memory chip select. These registers are normally only modified
during system initialization. These registers are accessed with one wait state.
Table5–86 shows the bit assignments for the EMCDynamicConfig0-3 registers.
Table 84. Dynamic Memory Load Mode register to Active Command Time
(EMCDynamictMRD - address 0xFFE0 8058) bit description
Bit Symbol Value Description Reset
Value
3:0 Load mode
register to active
command time
(tMRD)
0x0 -
0xE n + 1 clock cycles. The delay is in CCLK cycles. 0xF
0xF 16 clock cycles (POR reset value).
31:4 - - Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
NA
Table 85. Static Memory Extended Wait register (EMCStaticExtendedWait - address
0xFFE0 8080) bit description
Bit Symbol Value Description Reset
Value
9:0 Extended wait time
out
(EXTENDEDWAIT)
0x0 16 clock cycles (POR reset value). The delay is in
CCLK cycles.
0x1 (n+1) x16 clock cycles.
31:10 - - Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is
not defined.
NA