NXP Semiconductors UM10237 7.1.11 MII Mgmt Address Register (MADR - 0xFFE0 0028), 7.1.12 MII Mgmt Write Data Register (MWTD - 0xFFE0 002C), 7.1.13 MII Mgmt Read Data Register (MRDD - 0xFFE0 0030), 7.1.14 MII Mgmt Indicators Register (MIND - 0xFFE0 0034)

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User manual Rev. 02 — 19 December 2008 225 o f 792
NXP Semiconductors UM10237
Chapter 11: LPC24XX Ethernet
7.1.11 MII Mgmt Address Register (MADR - 0xFFE0 0028)
The MII Mgmt Address register (MADR) has an address of 0xFFE00028. The bit
definition of this register is shown in Table 11–199.
7.1.12 MII Mgmt Write Data Register (MWTD - 0xFFE0 002C)
The MII Mgmt Write Data register (MWTD) is a Write Only register with an address of
0xFFE0 002C. The bit definition of this register is shown in Table11–200.
7.1.13 MII Mgmt Read Data Register (MRDD - 0xFFE0 0030)
The MII Mgmt Read Data register (MRDD) is a Read Only register with an address of
0xFFE0 0030. The bit definition of this register is shown in Table11–201.
7.1.14 MII Mgmt Indicators Register (MIND - 0xFFE0 0034)
The MII Mgmt Indicators register (MIND) is a Read Only register with an address of
0xFFE0 0034. The bit definition of this register is shown in Table11–202.
Table 198. MII Mgmt Comman d reg i ster (MCMD - address 0xFFE00024 ) b it description
Bit Symbol Function Reset
value
0 READ This bit causes the MII Management ha rdware to perform a single Read cycle. The Read data is
returned in Register MRDD (MII Mgmt Read Data). 0
1 SCAN This bit causes the MII Management hardware to perform Read cycles continuou sl y. This is
useful for monitoring Link Fail for example. 0
31:2 - Unused 0x0
Table 199. MII Mg mt Address register (MADR - address 0xFFE0 0028) bit description
Bit Symbol Function Reset
value
4:0 REGISTER
ADDRESS This field represents the 5 bit Register Address field of Mgmt cycles. Up to 32 registers can be accessed. 0x0
7:5 - Unused 0x0
12:8 PHY ADDRESS This field represents the 5bit PHY Address field of Mgmt
cycles. Up to 31 PHYs can be addressed (0 is reserved). 0x0
31:13 - Unused 0x0
Table 200. MII Mgmt Write Data register (MWTD - address 0xFFE0 002C) bit descriptio n
Bit Symbol Function Reset
value
15:0 WRITE
DATA When written, an MII Mgmt write cycle is performed using the 16bit data and the pre-configured PHY and Register addresses from the
MII Mgmt Address register (MADR).
0x0
31:16 - Unused 0x0
Table 201. MII Mg mt Read Data register (MRDD - address 0xFFE00030) bit de scr iption
Bit Symbol Function Reset
value
15:0 READ
DATA Following an MII Mgmt Read Cycle, the 16bit data can be read from this location. 0x0
31:16 - Unused 0x0