UM10237_2 © NXP B.V. 2008. All rights reserved.
User manual Rev. 02 — 19 December 2008 558 o f 792
NXP Semiconductors UM10237
Chapter 21: LPC24XX SD/MMC card interface
•IDLE: The data path is inactive, and the MCIDAT[3:0] outputs are in HI-Z. When the
data control register is written and the enable bit is set, the DPSM loads the data
counter with a new value and, depending on the data direction bit, moves to either the
WAIT_S or WAIT_R state.
WAIT_R: If the data counter equals zero, the DPSM moves to the IDLE state when
the receive FIFO is empty. If the data counter is not zero, the DPSM waits for a start
bit on MCIDAT.
The DPSM moves to the RECEIVE state if it receives a start bit before a timeout, and
loads the data block counter. If it reaches a timeout before it detects a start bit, or a start
bit error occurs, it moves to the IDLE state and sets the timeout status flag.
•RECEIVE: Serial data received from a card is packed in bytes and written to the data
FIFO. Depending on the transfer mode bit in the data control register, the data transfer
mode can be either block or stream:
–In block mode, when the data block counter reaches zero, the DPSM waits until it
receives the CRC code. If the received code matches the internally generated
CRC code, the DPSM moves to the WAIT_R state. If not, the CRC fail status flag is
set and the DPSM moves to the IDLE state.
–In stream mode, the DPSM receives data while the data counter is not zero. When
the counter is zero, the remaining data in the shift register is written to the data
FIFO, and the DPSM moves to the WAIT_R state.
If a FIFO overrun error occurs, the DPSM sets the FIFO error flag and moves to the
WAIT_R state.
•WAIT_S: The DPSM moves to the IDLE state if the data counter is zero. If not, it waits
until the data FIFO empty flag is deasserted, and moves to the SEND state.
Fig 109. Data path state machine
IDLE
BUSY
SEND
WAIT_R
RECEIVE
WAIT_S
Reset
Disabled or
FIFO underrun or
end of data or
CRC fail
Disabled or
CRC fail or
timeout
Disabled or
end of data
Not busy
End of packet
Data ready
Enable
and send
Disabled or
Rx FIFO empty
or timeout or
start bit error
Enable and
not send Disabled or
CRC fail
Start bit
End of packet
or end of data
or FIFO overrun