NXP Semiconductors UM10237 4.16 UART1 Fractional Divider Register (U1FDR - 0xE001 0028)

UM10237_2 © NXP B.V. 2008. All rights reserved.
User manual Rev. 02 — 19 December 2008 461 o f 792
NXP Semiconductors UM10237
Chapter 17: LPC24XX Universal Asynchronous Receiver/Transmitter
4.16 UART1 Fractional Divider Register (U1FDR - 0xE001 0028)
The UART1 Fractional Divider Register (U1FDR) controls the clock pre-scaler for the
baud rate generation and can be read and written at the user’s discretion. This pre-scaler
takes the APB clock and generates an output clock according to the specified fractional
requirements.
Important: If the fractional divider is active (DIVADDVAL > 0) and DLM = 0, the value of
the DLL register must be 3 or greater.
a. Mode 0 (start bit and LSB are used for auto-baud)
b. Mode 1 (only start bit is used for auto-baud)
Fig 70. Auto-baud a) mode 0 and b) mode 1 waveform
UARTn RX start bit LSB of 'A' or 'a'
U0ACR start
rate counter
start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 parity stop
'A' (0x41) or 'a' (0x61)
16 cycles 16 cycles
16xbaud_rate
UARTn RX start bit LSB of 'A' or 'a'
rate counter
'A' (0x41) or 'a' (0x61)
start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 parity stop
U1ACR start
16 cycles
16xbaud_rate