UM10237_2 © NXP B.V. 2008. All rights reserved.
User manual Rev. 02 — 19 December 2008 135 o f 792
NXP Semiconductors UM10237
Chapter 8: LPC24XX Pin configuration
[1] 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis.
[2] 5 V tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input. When configured as a ADC input,
digital section of the pad is disabled.
[3] 5V tolerant pad providing digital I/O with TTL levels and hysteresis and analog out put function. When configured as the DAC output,
digital section of the pad is disabled.
[4] Open-drain 5 V tolerant digital I/O pad, compatible with I2C-bus 400 kHz specification. It requires an external pull-up to provide output
functionality. When power is switched off, this pin connected to the I2C-bus is floating and does not disturb the I2C lines. Open-drain
configuration applies to all functions on this pin.
[5] Pad provides digital I/O and USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and
Low-speed mode only).
[6] 5 V tolerant pad with 5ns glitch filter providing digital I/O functions with TTL levels and hyst eresis.
[7] 5 V tolerant pad with 20ns glitch filter providing dig ital I/O function with TTL levels and hysteresis.
[8] Pad provides special analog functionality.
[9] Pad provides special analog functionality.
[10] Pad pr ovides special analog functionality.
[11] Pad pr ovides special analog functionality.
[12] Pad pr ovides special analog functionality.
[13] Pad pr ovides special analog functionality.
[14] Pad pr ovides special analog functionality.
VSSIO H4, P4,
L9, L13,
G13,
D13,
C11,
B4[9]
Iground: 0 V reference for the digital IO pins.
VSSCORE H3, L8,
A10[9] Iground: 0 V reference for the core.
VSSA F3[10] Ianalog ground: 0 V reference. This should nominally be the same voltage as
VSSIO/VSSCORE, but should be isolated to minimize noise and error.
VDD(3V3) E2, L4,
K8, L11,
J14, E12,
E10,
C5[11]
I3.3 V supply voltage: This is the power supply voltage for the I/O ports.
n.c. H1, L12,
G10[12] Inot connected pins: These pins must be left unconnected (floating).
VDD(DCDC)(3V3) G1, N9,
E9[13] I3.3 V DC-to-DC converter supply voltage: This is the power supply for the
on-chip DC-to-DC converter.
VDDA F2[14] Ianalog 3.3 V pad supply voltage: This should be nominally the same voltage as
VDD(3V3) but should be isolated to minimize noise and error. This voltage is used
to power the ADC and DAC.
VREF G2[14] IADC reference: This should be nominally the same voltage as VDD(3V3) but
should be isolated to minimize noise and error. The level on this pin is used as a
reference for ADC and DAC.
VBAT K1[14] IRTC power supply: 3.3 V on this pin supplies the power to the RTC peripheral.
Table 120. Pin de scr iption …continued
Symbol Ball Type Description