UM10237_2 © NXP B.V. 2008. All rights reserved.
User manual Rev. 02 — 19 December 2008 762 o f 792
NXP Semiconductors UM10237
Chapter 36: LPC24XX Supplementary information
0xFFE0 8028) bit description . . . . . . . . . . . . . .81
Table 74. Dyn amic Memory Percentage Command Perio d
register (EMCDynamictRP - address
0xFFE0 8030) bit description . . . . . . . . . . . . . .82
Table 75. Dynamic Memory Active to Precharge Command
Period register (EMCDynamictRAS - address
0xFFE0 8034) bit description . . . . . . . . . . . . . .82
Table 76. Dynamic Memory Self-ref resh Exit Time register
(EMCDynamictSREX - address 0xFFE0 8038) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Table 77. Memory Last Data Out to Active Time register
(EMCDynamictAPR - address 0xFFE0 803C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Table 78. Dynamic Memory Data-in to Active Command
Time register (EMCDynamictDAL - address
0xFFE0 8040) bit description . . . . . . . . . . . . . .84
Table 79. Dynamic Memory Write recover Time register
(EMCDynamictWR - address 0xFFE0 8044) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Table 80. Dynamic Mempry Acti ve to Active Command
Period register (EMCDynamictRC - address
0xFFE0 8048) bit description . . . . . . . . . . . . . .85
Table 81. Dynamic Memory Auto-ref resh Period register
(EMCDynamictRFC - address 0xFFE0 804C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Table 82. Dynamic Memory Exit Self-ref resh register
(EMCDynamictXSR - address 0xFFE0 8050) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Table 83. Dynamic Memory Acitve Bank A to Active Bank B
Time register (EMCDynamictRRD - address
0xFFE0 8054) bit description . . . . . . . . . . . . . .86
Table 84. Dyn amic Memory Lo ad Mode register to Active
Command Time (EMCDynamictMRD - address
0xFFE0 8058) bit description . . . . . . . . . . . . . .87
Table 85. Static Memory Extended Wait register
(EMCStaticExtendedWait - address
0xFFE0 8080) bit description . . . . . . . . . . . . . .87
Table 86. Dynamic Memory Confi guration registers
(EMCDynamicConfig0-3 - address 0xFFE0 8100,
0xFFE0 8120, 0xFFE0 8140, 0xFFE0 8160) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
Table 87. Address mapping . . . . . . . . . . . . . . . . . . . . . . .88
Table 88. Dynamic Memory RAS & CAS Delay registers
(EMCDynamicRasCas0-3 - address
0xFFE0 8104, 0xFFE0 8124, 0xFFE0 8144,
0xFFE0 8164) bit description . . . . . . . . . . . . . .90
Table 89. Static Memory Configuration registers
(EMCStaticConfig0-3 - address 0xFFE0 8200,
0xFFE0 8220, 0xFFE0 8240, 0xFFE0 8260) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
Table 90. Static Memory Write Enable Delay registers
(EMCStaticWaitWen0-3 - address
0xFFE0 8204,0xFFE0 8224, 0xFFE0 8244,
0xFFE0 8264) bit description . . . . . . . . . . . . . .93
Table 91. Static Memory Output Enable delay registers
(EMCStaticWaitOen03 - address 0xFFE08208,
0xFFE0 8228, 0xFFE0 8248, 0xFFE0 8268) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
Table 92. Static Memory Read Delay registers
(EMCStaticWaitRd0-3 - address 0xFFE0820C,
0xFFE0 822C, 0xFFE0 824C, 0xFFE0 826C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
Table 93. Static Memory Page Mode Read Delay
registers0-3 (EMCStaticWaitPage0-3 - address
0xFFE0 8210, 0xFFE0 8230, 0xFFE0 8250,
0xFFE0 8270) bit description. . . . . . . . . . . . . . 94
Table 94. Static Memory Write Delay registers0-3
(EMCStaticWaitWr - address 0xFFE08214,
0xFFE0 8234, 0xFFE0 8254, 0xFFE0 8274) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
Table 95. Static Memory Trun Round Delay registers0-3
(EMCStaticWaitTurn0-3 - address 0xFFE08218,
0xFFE0 8238, 0xFFE0 8258, 0xFFE0 8278) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
Table 96. MAM responses to program accesses of va rious
types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
Table 97. MAM responses to data and DMA accesses of
various types . . . . . . . . . . . . . . . . . . . . . . . . .103
Table 98. Su mmary of Memory Acceleration Module
registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table 99. MAM Control Reg ister (MAMCR - address
0xE01F C000) bit description. . . . . . . . . . . . .104
Table 100.MAM Timing register (MAMTIM - address
0xE01F C004) bit description. . . . . . . . . . . . .105
Table 101.Suggestions for MAM timing selection. . . . . . 107
Table 102.Summary of VIC registers . . . . . . . . . . . . . . .109
Table 103.Software Interrupt register (VICSoftInt - address
0xFFFF F018) bit description. . . . . . . . . . . . . 111
Table 104.Software Interrupt Clear register (VICSoftIntClear
- address 0xFFFF F01C) bit description . . . . 111
Table 105.Raw Interrupt Status register (VICRawIntr -
address 0xFFFF F008) bit description. . . . . . 112
Table 106.Interrupt Enable register (VICIntEnable - address
0xFFFF F010) bit description. . . . . . . . . . . . . 112
Table 107.Interrupt Enable Clear register (VICIntEnClear -
address 0xFFFF F014) bit description. . . . . . 112
Table 108.Interrupt Select register (VICIntSelect - address
0xFFFF F00C) bit description . . . . . . . . . . . . 113
Table 109.IRQ Status register (VICIRQStatus - address
0xFFFF F000) bit description. . . . . . . . . . . . . 113
Table 110.FIQ Status register (VICFIQStatus - address
0xFFFF F004) bit description. . . . . . . . . . . . . 113
Table 111.Vector Address registers 0-31 (VICVectAddr0-31 -
addresses 0xFFFF F100 to 0xFFFF F17C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Table 112.Vector Priority registers 0-31 (VICVectPriority0-31
- addresses 0xFFFF F200 to 0xFFFF F27C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Table 113.Vector Address register (VICAddress - address
0xFFFF FF00) bit description. . . . . . . . . . . . . 114
Table 114.Software Priority Mask register
(VICSWPriorityMask - address 0xFFFF F024) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Table 115.Protection Enable register (VICProtection -
address 0xFFFF F020) bit description. . . . . . 115
Table 116.Connection of interrupt sources to the Vectored