UM10237_2 © NXP B.V. 2008. All rights reserved.
User manual Rev. 02 — 19 December 2008 60 of 792
NXP Semiconductors UM10237
Chapter 4: LPC24XX Clocking and power control
In Idle mode, execution of instructions is suspended until either a Reset or interrupt
occurs. Peripheral functions continue operation during Idle mode and may generate
interrupts to cause the processor to resume execution. Idle mode eliminates dynamic
power used by the processor itself, memory systems and related controllers, and internal
buses.
3.4.2 Sleep mode
When the chip enters the Sleep mode, the main oscillator is powered down and all clocks
are stopped. The output of the IRC is disabled but the IRC is not powered down for a fast
wakeup later. The 32 kHz RTC oscillator is not stopped because the RTC interrupts may
be used as the wakeup source. The Flash is left in the standby mode allowing a very quick
wakeup. The PLL is automatically turned off and disconnected. The CCLK and USBCLK
clock dividers automatically get reset to zero.
The processor state and registers, peripheral registers, and internal SRAM values are
preserved throughout Sleep mode and the logic levels of chip pins remain static. The
Sleep mode can be terminated and normal operation resumed by either a Reset or certain
specific interrupts that are able to function without clocks. Since all dynamic operation of
the chip is suspended, Sleep mode reduces chip power consumption to a very low value.
On the wakeup of sleep mode, if the IRC was used before entering sleep mode, the 2-bit
IRC timer starts counting and the code execution and peripherals activities will resume
after the timer expires (4 cycles). If the main external oscillator was used, the 12-bit main
oscillator timer starts counting and the code execution will resume when the timer expires
(4096 cycles). Customer must not forget to re-configure the PLL and clock dividers after
the wakeup.
3.4.3 Power-down mode
Power-down mode does everything that Sleep mode does, but also turns off the Flash
memory. This saves more power, but requires waiting for resumption of Flash operation
before execution of code or data access in the Flash memory can be accomplished.
When the chip enters power-down mode, the IRC, the main oscillator and all clocks are
stopped. The 32Khz RTC oscillator is not stopped because the RTC interrupts may be
used as the wakeup source. The flash is forced into power-down mode. The PLL is
automatically turned off and disconnected. The CCLK and USBCLK clock dividers
automatically get reset to zero.
On the wakeup of power-down mode, if the IRC was used before entering power-down
mode, after IRC-start-up time (60 μs), the 2-bit IRC timer starts counting and expires in 4
cycles. The code execution can then be resumed immediately upon the expiration of the
IRC timer if the code was running from SRAM. In the meantime, the Flash wakeup-timer
generates Flash start-up time 100 μs. When it times out, access to the Flash is enabled.
Customer must not forget to re-configure the PLL and clock dividers after the wakeup.
3.4.4 Peripheral power control
A Power Control for Peripherals feature allows individual peripherals to be turned off if
they are not needed in the application, resulting in additional power savings. This is
detailed in the description of the PCONP register.