NXP Semiconductors UM10237 3.4 Power control

UM10237_2 © NXP B.V. 2008. All rights reserved.
User manual Rev. 02 — 19 December 2008 59 of 792
NXP Semiconductors UM10237
Chapter 4: LPC24XX Clocking and power control
[1] For PCLK_RTC only, the value ’01’ is illegal. Do not write ’01’ to the PCLK_RTC. Attempting to write ’01’
results in the previous value being unchanged.
3.4 Power control
The LPC2400 supports a variety of power control features. There are three special modes
of processor power reduction: Idle mode, Sleep mode, and Power-down mode. The CPU
clock rate may also be controlled as needed by changing clock sources, re-configuring
PLL values, and/or altering the CPU clock divider value. This allows a trade-off of power
versus processing speed based on application requirements. In addition, Peripheral
Power Control allows shutting down the clocks to individual on-chip peripherals, allowing
fine tuning of power consumption by eliminating all dynamic power use in any peripherals
that are not required for the application.
The LPC2400 also implements a separate power domain in order to allow turning off
power to the bulk of the device while maintaining operation of the Real Time Clock and a
small static RAM, referred to as the Battery RAM. This feature is described in more detail
later in this chapter under the heading Power Domains, and in the Real Time Clock and
Battery RAM chapter.
3.4.1 Idle mode
When Idle mode is entered, the clock to the core is stopped. Resumption from the Idle
mode does not need any special sequence but re-enabling the clock to the ARM core.
13:12 PCLK_TIMER2 Peripheral clock selection for TIMER2. 00
15:14 PCLK_TIMER3 Peripheral clock selection for TIMER3. 00
17:16 PCLK_UART2 Peripheral clock selection for UART2. 00
19:18 PCLK_UART3 Peripheral clock selection for UART3. 00
21:20 PCLK_I2C2 Peripheral clock selection for I2C2. 00
23:22 PCLK_I2S Peripheral clock selection for I2S. 00
25:24 PCLK_MCI Peripheral clock selection for MCI. 00
27:26 - Unused, always read as 0. 00
29:28 PCLK_SYSCON Peripheral clock selection for the System Control block. 00
31:30 - Unused, always read as 0. 00
Table 58. Peripheral Clock Selection register bit values
PCLKSEL0 and PCLKSEL1
individual peripheral’s clock
select options
Function Reset
value
00 PCLK_xyz = CCLK/4 00
01 PCLK_xyz = CCLK[1]
10 PCLK_xyz = CCLK/2
11 Peripheral’s clock is selected to PCLK_xyz = CCLK/8
except for CAN1, CAN2, and CAN filtering when ’11’
selects PCLK_xyz = CCLK/6.
Table 57. Peripheral Clock Selection register 1 (PCLKSEL1 - address 0xE01F C1AC) bit
description
Bit Symbol Description Reset
value