UM10237_2 © NXP B.V. 2008. All rights reserved.
User manual Rev. 02 — 19 December 2008 773 o f 792
NXP Semiconductors UM10237
Chapter 36: LPC24XX Supplementary information
4. Figures
Fig 1. LPC2458 block diagram . . . . . . . . . . . . . . . . . . .11
Fig 2. LPC2460 block diagram . . . . . . . . . . . . . . . . . . .12
Fig 3. LPC2468 block diagram . . . . . . . . . . . . . . . . . . .13
Fig 4. LPC2470 block diagram . . . . . . . . . . . . . . . . . . .14
Fig 5. LPC2478 block diagram . . . . . . . . . . . . . . . . . . .15
Fig 6. LPC2400 system memory map . . . . . . . . . . . . . .19
Fig 7. Peripheral memory map. . . . . . . . . . . . . . . . . . . .20
Fig 8. AHB peripheral map . . . . . . . . . . . . . . . . . . . . . .21
Fig 9. Map of lower memory is showing re-mapped and
re-mappable areas for a LPC2400 part with flash26
Fig 10. Reset blo ck diagram including the wakeup timer.33
Fig 11. Example of start-up after reset. . . . . . . . . . . . . . .34
Fig 12. Clo ck generation for the LPC2400. . . . . . . . . . . .42
Fig 13. Oscil lator modes and models: a) slave mode of
operation, b) oscillation mode of operation, c)
external crystal model used for CX1/X2 evaluation44
Fig 14. PLL bl ock diagram (N = 16, M = 125, USBSEL = 6,
CCLKSEL = 4). . . . . . . . . . . . . . . . . . . . . . . . . . .47
Fig 15. EMC block diagram . . . . . . . . . . . . . . . . . . . . . . .69
Fig 16. 32 bi t ban k external memory interfaces ( bits
MW = 10). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
Fig 17. 16 bi t ban k external memory interfaces (bits
MW = 01). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
Fig 18. 8 bit bank external memory interface
(bits MW =0 0) . . . . . . . . . . . . . . . . . . . . . . . . . . .98
Fig 19. Typical memory configuration di ag ram . . . . . . . .99
Fig 20. Simplified block diagram of the Memory Accelerator
Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Fig 21. Block diagram of the Memory Accelerat or Module .
106
Fig 22. Block dia gram of the Vectored Interrupt Controller .
118
Fig 23. LPC24 58 pinning TFBGA180 package . . . . . . .119
Fig 24. LPC24 00 pinning LQFP208 package . . . . . . . . 120
Fig 25. LPC24 00 pinning TFBGA208 package . . . . . . .120
Fig 26. Ethernet block diagram . . . . . . . . . . . . . . . . . . .212
Fig 27. Ethernet packet fields . . . . . . . . . . . . . . . . . . . .216
Fig 28. Receive descriptor memory layout. . . . . . . . . . .241
Fig 29. Transmit descriptor memory layout . . . . . . . . . .244
Fig 30. Transmit example memory and registers . . . . . .255
Fig 31. Recei ve Example Memory and Registers . . . . .261
Fig 32. Transmit Flow Control . . . . . . . . . . . . . . . . . . . .266
Fig 33. Recei ve filter block diagram. . . . . . . . . . . . . . . .268
Fig 34. Receive Active/Inactive state machine . . . . . . .272
Fig 35. Transmit Active/Inactive state machine . . . . . . .273
Fig 36. LCD controller block diagram. . . . . . . . . . . . . . .286
Fig 37. Cursor movement . . . . . . . . . . . . . . . . . . . . . . .294
Fig 38. Cursor clipping . . . . . . . . . . . . . . . . . . . . . . . . . .295
Fig 39. Cursor image format . . . . . . . . . . . . . . . . . . . . .296
Fig 40. Power up and power down sequences . . . . . . .302
Fig 41. Horizontal timing for STN displays. . . . . . . . . . .322
Fig 42. Vertical timing for STN displays . . . . . . . . . . . . .323
Fig 43. Horizontol timing for TFT displays . . . . . . . . . . .323
Fig 44. Vertical timing for TFT displays . . . . . . . . . . . . .324
Fig 45. USB device control ler block diagram. . . . . . . . .331
Fig 46. USB MaxPacketSize register array indexing. . .349
Fig 47. I nterrupt event handling . . . . . . . . . . . . . . . . . .361
Fig 48. UDCA Head register and DMA Descriptors . . . 374
Fig 49. Isochrono us OUT endpoint operation example. 382
Fig 50. Data transfer in ATLE mode . . . . . . . . . . . . . . . 383
Fig 51. USB Host contro ller blo ck diagram. . . . . . . . . . 389
Fig 52. USB OT G cont roller block diagram. . . . . . . . . . 394
Fig 53. USB OTG port configuration: port U1 OTG
Dual-Role device, port U2 host. . . . . . . . . . . . . 396
Fig 54. USB OT G port configuration: VP_VM mode. . . 397
Fig 55. USB OT G port configuration: port U2 host, port U1
host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .398
Fig 56. USB OT G port configuration: port U1 host, port U2
device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .399
Fig 57. Port selection f or PORT_FUNC bit 0 = 0 and
PORT_FUNC bit 1 = 0.. . . . . . . . . . . . . . . . . . . 403
Fig 58. USB OTG interrupt handling . . . . . . . . . . . . . . .409
Fig 59. USB OTG cont roller with software stack. . . . . . 411
Fig 60. Hardware supp ort f or B-device switching from
peripheral state to host state . . . . . . . . . . . . . .412
Fig 61. State transitions implemented in software during
B-device switching from peripheral to host . . . . 413
Fig 62. Hardware supp ort f or A-device switching from host
state to peripheral state. . . . . . . . . . . . . . . . . . . 415
Fig 63. State transitions implemented in software during
A-device switching from host to peripheral . . . . 416
Fig 64. Clocking and power control. . . . . . . . . . . . . . . . 419
Fig 65. Aut obaud a) mode 0 and b) mode 1 waveform 436
Fig 66. Algorithm for setting UART dividers . . . . . . . . .439
Fig 67. UART0, 2 and 3 block diagra m . . . . . . . . . . . . . 442
Fig 68. Auto-RTS Functional Timing . . . . . . . . . . . . . . .454
Fig 69. Auto-CTS Functional Timing . . . . . . . . . . . . . . .455
Fig 70. Aut o-baud a) mode 0 and b) mode 1 waveform 461
Fig 71. Algorithm for setting UART dividers . . . . . . . . .463
Fig 72. UART1 block diagram . . . . . . . . . . . . . . . . . . . .466
Fig 73. CAN controller block diagram . . . . . . . . . . . . . . 469
Fig 74. Transmit buffer layout for standard and extended
frame format configurations . . . . . . . . . . . . . . . 470
Fig 75. Recei ve buffer layout for standard and extended
frame format configurations . . . . . . . . . . . . . . . 471
Fig 76. Globa l Self-Test (high-speed CAN
Bus example) . . . . . . . . . . . . . . . . . . . . . . . . . . 472
Fig 77. Local self test (high-sp eed CAN Bus example). 472
Fig 78. Ent ry in Ful lCAN and individual standard identifier
tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .499
Fig 79. Entry in standard identifier range table . . . . . . . 499
Fig 80. Entry in either extended identifier table. . . . . . . 499
Fig 81. ID Look-up table example explaining the search
algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .507
Fig 82. Semaphore proce dure for reading an auto-stored
message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .510
Fig 83. FullCAN section example of the ID look-up
table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .512
Fig 84. FullCAN message object layout . . . . . . . . . . . .512
Fig 85. Normal case, no messages lost . . . . . . . . . . . .514
Fig 86. Message lost . . . . . . . . . . . . . . . . . . . . . . . . . . .514
Fig 87. Message gets overwritten . . . . . . . . . . . . . . . . .515