NXP Semiconductors UM10237 7.3 SPI Data Register (S0SPDR - 0xE002 0008), 7.4 SPI Clock Counter Register (S0SPCCR - 0xE002 000C), 7.5 SPI Test Control Register (SPTCR

User manual Rev. 02 — 19 December 2008 533 o f 792

NXP Semiconductors UM10237

Chapter 19: LPC24XX SPI

7.3 SPI Data Register (S0SPDR - 0xE002 0008)

This bi-directional data register provides the transmit and receive data for the SPI.

Transmit data is provided to the SPI by writing to this register. Data received by the SPI

can be read from this register. When a master, a write to this register will start a SPI data

transfer. Writes to this register will be blocked from when a data transfer starts to when the

SPIF status bit is set, and the status register has not been read.

7.4 SPI Clock Counter Register (S0SPCCR - 0xE002 000C)

This register controls the frequency of a master’s SCK. The register indicates the number

of SPI peripheral clock cycles that make up an SPI clock.

In Master mode, this register must be an even number greater than or equal to 8.

Violations of this can result in unpredictable behavior. The SPI0 SCK rate may be

calculated as: PCLK_SPI / SPCCR0 value. The SPI peripheral clock is determined by the

PCLKSEL0 register contents for PCLK_SPI.

In Slave mode, the SPI clock rate provided by the master must not exceed 1/8 of the SPI

peripheral clock selected in Section 4–3.3.4. The content of the S0SPCCR register is not

relevant.

7.5 SPI Test Control Register (SPTCR - 0xE002 0010)

Note that the bits in this register are intended for functional verification only. This register

should not be used for normal operation.

5 ROVR Read overrun. When 1, this bit indicates that a read overrun has

occurred. This bit is cleared by reading this register. 0

6 WCOL Write collision. When 1, this bit indicates that a wri te collision has

occurred. This bit is cleared by reading this register, then

accessing the SPI data register.

7 SPIF SPI transfer complete flag. When 1, this bit indicates when a SPI

data transfer is complete. When a master, this bit is set at the

end of the last cycle of the transfer. When a slave, this bit is set

on the last data sampling edge of the SCK. This bit is cleared by

first reading this register, then accessing the SPI data register.

Note: this is not the SPI interrupt flag. This flag is found in the

SPINT register.

Table 463: SPI Status Register (S0SPSR - address 0xE002 0004) bit description

Bit Symbol Description Reset Value

Table 464: SPI Data Register (S0SPDR - address 0xE002 0008) bit description

Bit Symbol Description Reset Value

7:0 DataLow SPI Bi-directional data port. 0x00

15:8 DataHigh If bit 2 of the SPCR is 1 and bits 11:8 are other than 1000, some

or all of these bits contain the additional transmit and receive

bits. When less than 16 bits are selected, the more significant

among these bits read as zeroes.

0x00

Table 465: SPI Clock Counter Register (S0SPCCR - address 0xE002 000C) bit description

Bit Symbol Description Reset Value

7:0 Counter SPI0 Clock counter setting. 0x00