UM10237_2 © NXP B.V. 2008. All rights reserved.
User manual Rev. 02 — 19 December 2008 62 of 792
NXP Semiconductors UM10237
Chapter 4: LPC24XX Clocking and power control
Encoding of Reduced Power Modes
The PM2, PM1, and PM0 bits in PCON allow entering reduced power modes as needed.
The encoding of these bits allows backward compatibility with devices that previously only
supported Idle and Power-down modes. Tabl e 4–6 1 below shows the encoding for the
three reduced power modes supported by the LPC2400.
3.4.7 Interrupt Wakeup Register (INTWAKE - 0xE01F C144)
Enable bits in the INTWAKE register allow the external interrupts to wake up the
processor if it is in Power-down mode. The related EINTn function must be mapped to the
pin in order for the wakeup process to take place. It is not necessary for the interrupt to be
enabled in the Vectored Interrupt Controller for a wakeup to take place. This arrangement
allows additional capabilities, such as having an external interrupt input wake up the
processor from Power-down mode without causing an interrupt (simply resuming
operation), or allowing an interrupt to be enabled during Power-down without waking the
processor up if it is asserted (eliminating the need to disable the interrupt if the wakeup
feature is not desirable in the application). Details of the wakeup operations are shown in
Table4–62.
For an external interrupt pin to be a source that would wake up the microcontroller from
Power-down mode, it is also necessary to clear the corresponding interrupt flag (see
Section 3–3.1.2 “External Interrupt flag register (EXTINT - 0xE01F C140)”).
4 BORD Brown-Out Reset Disable. When BORD is 1, the second stage of low
voltage detection (2.6 V) will not cause a chip reset.
When BORD is 0, the reset is enabled. The first stage of low voltage
detection (2.9 V) Brown-Out interrupt is not affected.
See the System Control Block chapter for details of Brown-Out
detection.
0
6:3 - Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined. NA
7 PM2 Power mode control bit 2. See text and table below for details. 0
Table 61. Encoding of reduced power modes
PM2, PM1, PM0 Description
000 Normal operation
001 Idle mode. Causes the processor clock to be stopped, while on-chip peripherals
remain active. Any enabled interrupt from a peripheral or an external interrupt
source will cause the processor to resume execution. See text for details.
101 Sleep mode. This mode is similar to Power-down mode (the oscillator and all
on-chip clocks are stopped), but the Flash memory is left in Standby mode. This
allows a more rapid wakeup than Power-down mode because the Flash
reference voltage regulator start-up time is not needed. See text for details.
010 Power-down mode. Causes the oscillator and all on-chip clocks to be stopped.
A wakeup condition from an external interrupt can cause the oscillator to
re-start, the PD bit to be cleared, and the processor to resume execution. See
text for details.
Others Reserved, not currently used.
Table 60. Power Mode Control register (PCON - address 0xE01F C0C0) bit description
Bit Symbol Description Reset
value