NXP Semiconductors UM10237 6.14 FIFO Counter Register (MCIFifoCnt - 0xE008 C048), 6.15 Data FIFO Register (MCIFIFO - 0xE008 C080 to 0xE008 C0BC)

UM10237_2 © NXP B.V. 2008. All rights reserved.
User manual Rev. 02 — 19 December 2008 571 o f 792
NXP Semiconductors UM10237
Chapter 21: LPC24XX SD/MMC card interface
6.14 FIFO Counter Register (MCIFifoCnt - 0xE008 C048)
The MCIFifoCnt register contains the remaining number of words to be written to or read
from the FIFO. The FIFO counter loads the value from the data length register (see
Section 21–6.8 “Data Length Register (MCIDataLength - 0xE008 C028)”) when the
Enable bit is set in the data control register. If the data length is not word aligned (multiple
of 4), the remaining 1 to 3 bytes are regarded as a word. Table21–507 shows the bit
assignment of the MCIFifoCnt register.
6.15 Data FIFO Register (MCIFIFO - 0xE008 C080 to 0xE008 C0BC)
The receive and transmit FIFOs can be read or written as 32 bit wide registers. The FIFOs
contain 16 entries on 16 sequential addresses. This allows the microprocessor to use its
load and store multiple operands to read/write to the FIFO. Table21–508 shows the bit
assignment of the MCIFIFO register.
8 Mask8 Mask DataEnd flag. 0
9 Mask9 Mask StartBitErr flag. 0
10 Mask10 Mask DataBlockEnd flag. 0
11 Mask11 Mask CmdActive flag. 0
12 Mask12 Mask TxActive flag. 0
13 Mask13 Mask RxActive flag. 0
14 Mask14 Mask TxFifoHalfEmpty flag. 0
15 Mask15 Mask RxFifoHalfFull flag. 0
16 Mask16 Mask TxFifoFull flag. 0
17 Mask17 Mask RxFifoFull flag. 0
18 Mask18 Mask TxFifoEmpty flag. 0
19 Mask19 Mask RxFifoEmpty flag. 0
20 Mask20 Mask TxDataAvlbl flag. 0
21 Mask21 Mask RxDataAvlbl flag. 0
31:22 - Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined. NA
Table 506: Interrupt Mask registers (MCIMask0 - address 0xE008 C03C) bit description
Bit Symbol Description Reset
Value
Table 507: FIFO Counter register (MCIFifoCnt - address 0xE008 C048) bit description
Bit Symbol Description Reset
Value
14:0 DataCount Remaining data 0x0000
31:15 - Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined. NA
Table 508: Data FIFO register (MCIFIFO - address 0xE008 C080 to 0xE008 C0BC) bit
description
Bit Symbol Description Reset Value
31:0 Data FIFO data. 0x0000 0000