NXP Semiconductors UM10237 10.6 Dynamic Memory Read Configuration register (EMCDynamicReadConfig - 0xFFE0 8028), 10.7 Dynamic Memory Percentage Command Period register (EMCDynamictRP - 0xFFE0 8030)

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User manual Rev. 02 — 19 December 2008 81 of 792
NXP Semiconductors UM10237
Chapter 5: LPC24XX External Memory Controller (EMC)
10.6 Dynamic Memory Read Configuration register
(EMCDynamicReadConfig - 0xFFE0 8028)
The EMCDynamicReadConfig register configures the dynamic memory read strategy.
This register must only be modified during system initialization. This register is accessed
with one wait state.
Note: This register is used for all four dynamic memory chip selects. Therefore the worst
case value for all of the chip selects must be programmed.
Important: Especially it should be highlighted that the default clock delay methodology
requires the output clock to be delayed externally to the chip to avoid hold time issue for
the SDRAM. In most application boards, there will be no such external delay circuit and
the application should write correct value to the EMCDynamicReadConfig register to use
Command Delay Strategy. The Clock Delay Strategy is the default setting on reset!
Table5–73 shows the bit assignments for the EMCDynamicReadConfig register.
10.7 Dynamic Memory Percentage Command Period register
(EMCDynamictRP - 0xFFE0 8030)
The EMCDynamicTRP register enables you to program the precharge command period,
tRP. This register must only be modified during system initialization. This value is normally
found in SDRAM data sheets as tRP. This register is accessed with one wait state.
Note: This register is used for all four dynamic memory chip selects. Therefore the worst
case value for all of the chip selects must be programmed.
Table5–74 shows the bit assignments for the EMCDynamicTRP register.
Table 73. Dynamic Memory Read Configuration register (EMCDynamicReadConfig -
address 0xFFE0 8028) bit description
Bit Symbol Value Description Reset
Value
1:0 Read data
strategy (RD) 00 Clock out delayed strategy, using CLKOUT (command not delayed, clock out delayed). POR reset value. 0x0
01 Comma nd delayed strategy, using EMCCLKDELAY
(command delayed, clock out not delayed).
10 Command delayed strategy plus one clock cycle, using
EMCCLKDELAY (command delayed, clock out not
delayed).
11 Comma nd del ayed strategy plus two clock cycles, using
EMCCLKDELAY (command delayed, clock out not
delayed).
31:2 - - Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
NA