UM10237_2 © NXP B.V. 2008. All rights reserved.
User manual Rev. 02 — 19 December 2008 52 of 792
NXP Semiconductors UM10237
Chapter 4: LPC24XX Clocking and power control
connected for use. The value of PLOCK may not be stable when the PLL reference
frequency (FREF, the frequency of REFCLK, which is equal to the PLL input frequency
divided by the pre-divider value) is less than 100 kHz or greater than 20 MHz. In these
cases, the PLL may be assumed to be stable after a start-up time has passed. This time is
500 μs when FREF is greater than 400 kHz and 200 / FREF seconds when FREF is less
than 400 kHz
PLOCK is connected to the interrupt controller. This allows for software to turn on the PLL
and continue with other functions without having to wait for the PLL to achieve lock. When
the interrupt occurs, the PLL may be connected, and the interrupt disabled.
3.2.8 PLL Modes
The combinations of PLLE and PLLC are shown in Table 4–48.
3.2.9 PLL Feed register (PLLFEED - 0xE01F C08C)
A correct feed sequence must be written to the PLLFEED register in order for changes to
the PLLCON and PLLCFG registers to take effect. The feed sequence is:
1. Write the value 0xAA to PLLFEED.
2. Write the value 0x55 to PLLFEED.
The two writes must be in the correct sequence, and must be consecutive APB bus
cycles. The latter requirement implies that interrupts must be disabled for the duration of
the PLL feed operation. If either of the feed values is incorrect, or one of the previously
mentioned conditions is not met, any changes to the PLLCON or PLLCFG register will not
become effective.
3.2.10 PLL and Power-down mode
Power-down mode automatically turns off and disconnects the PLL. Wakeup from
Power-down mode does not automatically restore the PLL settings, this must be done in
software. Typically, a routine to activate the PLL, wait for lock, and then connect the PLL
can be called at the beginning of any interrupt service routine that might be called due to
the wakeup. It is important not to attempt to restart the PLL by simply feeding it when
execution resumes after a wakeup from Power-down mode. This would enable and
connect the PLL at the same time, before PLL lock is established.
Table 48. PLL control bit combinations
PLLC PLLE PLL Function
0 0 PLL is turned off and disconnected. The PLL outputs the unmodified clock
input.
0 1 The PLL is active, but not yet connected. The PLL can be connected after
PLOCK is asserted.
1 0 Same as 00 combination. This prevents the possibility of the PLL being
connected without also being enabled.
1 1 The PLL is active and has been connected as the system clock source.
Table 49. PLL Feed register (PLLFEED - address 0xE01F C08C) bit description
Bit Symbol Description Reset
value
7:0 PLLFEED The PLL feed sequence must be written to this register in order for
PLL configuration and control register changes to take effect. 0x00