NXP Semiconductors UM10237 user manual

UM10237_2 © NXP B.V. 2008. All rights reserved.
User manual Rev. 02 — 19 December 2008 53 of 792
NXP Semiconductors UM10237
Chapter 4: LPC24XX Clocking and power control
3.2.11 PLL frequency calculation
The PLL equations use the following parameters:
The PLL output frequency (when the PLL is both active and connected) is given by:
FCCO = (2 × M × FIN) / N
The PLL inputs and settings must meet the following:
•FIN is in the range of 32 kHz to 50 MHz.
•FCCO is in the range of 275 MHz to 550 MHz.
The PLL equation can be solved for other PLL parameters:
M = (FCCO × N) / (2 × FIN)
N = (2 × M × FIN) / FCCO
FIN = (FCCO × N) / (2 × M)
Allowed values for M:
At higher oscillator frequencies, in the MHz range, values of M from 6 through 512 are
allowed. This supports the entire useful range of both the main oscillator and the IRC.
For lower frequencies, specifically when the RTC is used to clock the PLL, a set of 65
additional M values have been selected for supporting baud rate generation, CAN/USB
operation, and attaining even MHz frequencies. These values are shown in Table4–51
Table 50. PLL frequency parameter
Parameter Description
FIN the frequency of pllclkin from the Clock Source Selection Multiplexer.
FCCO the frequency of the pllclk (output of the PLL Current Controlled Oscillator)
N PLL Pre-divider value from the NSEL bits in the PLLCFG register (PLLCFG
NSEL field + 1). N is an integer from 1 through 32.
M PLL Multiplier value from the MSEL bits in the PLLCFG register (PLLCFG
MSEL field + 1). Not all potential values are supported. See below.
FREF PLL internal reference frequency, FIN divided by N.
Table 51. Additional Multiplier Values for use with a Low Frequency Clock Input
Low Frequency PLL Multipliers
4272 4395 4578 4725 4807
5127 5188 5400 5493 5859
6042 6075 6104 6409 6592
6750 6836 6866 6958 7050
7324 7425 7690 7813 7935
8057 8100 8545 8789 9155
9613 10254 10376 10986 11719
12085 12207 12817 13184 13672
13733 13916 14099 14420 14648
15381 15564 15625 15869 16113