NXP Semiconductors UM10237

User manual Rev. 02 — 19 December 2008 479 o f 792

Chapter 18: LPC24XX CAN controllers CAN1/2

[1] After reading all messages and releasing their memory space with the command 'Release Receive Buffer,' this bit is cleared.

[2] If there is not enough space to store the message within the Receive Buffer, that message is dropped and the Data Overrun condition is

signalled to the CPU in the moment this message becomes valid. If this message is not completed successfully (e.g. because of an

error), no overrun condition is signalled.

[3] The Transmission Complete Status bit is set '0' (incomplete) whenever the Transmission Request bit or the Self Reception Request bit

is set '1' at least for one of the three Transmit Buffers. The Transmission Complete Status bit will remain '0' until all messages are

transmitted successfully.

[4] If both the Receive Status and the Transmit Status bits are '0' (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to

become idle again. After hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. After Bus-off this

will take 128 times of 11 consecutive recessive bits.

[5] Errors detected during reception or transmission will effect the error counters according to the CAN specification. The Error Status bit is

set when at least one of the error counters has reached or exceeded the Error Warning Limit. An Error Warning Interrupt is generated, if

enabled. The default value of the Error Warning Limit after hardware reset is 96 decimal, see also Section 18–8.7 “Error Warning Limit

[6] Mode bit '1' (present) and an Error Warning Interrupt is generated, if enabled. Afterwards the Transmit Error Counter is set to '127', and

the Receive Error Counter is cleared. It will stay in this mode until the CPU clears the Reset Mode bit. Once this is completed the CAN

Controller will wait the minimum protocol-defined time (128 occurrences of the Bus-Free signal) counting down the Transmit Error

Counter. After that, the Bus Status bit is cleared (Bus-On), the Error Status bit is set '0' (ok), the Error Counters are reset, and an Error

Warning Interrupt is generated, if enabled. Reading the TX Error Counter during this time gives information about the status of the

Bus-Off recovery.

RX error counterThe RX Error Counter Register, which is part of the Status Register, reflects the current value of the Receive Error Counter. After hardware reset this register is initialized to 0. In Operating Mode this register appears to the CPU as a read only memory. A write access to this register is possible only in Reset Mode. If a Bus Off event occurs, the RX Error Counter is initialized to 0. As long as Bus Off is valid, writing to this register has no effect.The Rx Error Counter is determined as follows:

4RS

[4] Receive Status. 1 0

0 (idle) The CAN controller is idle.

1 (receive) The CAN controller is receiving a message.

5TS

[4] Transmit Status. 1 0

0 (idle) The CAN controller is idle.

1 (transmit) The CAN controller is sending a message.

6ES

[5] Error Status. 0 0

0 (ok) Both error counters are below the Error Warning Limit.

1 (error) One or both of the Transmit and Receive Error Counters has reached the

limit set in the Error Warning Limit register.

7BS

[6] Bus Status. 0 0

0 (Bus-On) The CAN Controller is involved in bus activities

1 (Bus-Off) The CAN controller is currently not involved/prohibited from bus activity

because the Transmit Error Counter reached its limiting value of 255.

15:8 - - Reserved, user software should not write ones to reserved bits. The value

read from a reserved bit is not defined. NA

23:16 RXERR - The current value of the Rx Error Counter (an 8 - bit value). 0 X

31:24 TXERR - The current valu e of the Tx Error Counter (an 8- bit value). 0 X

Table 422. Global Status Register (CAN1GSR - address 0xE004 4008, CAN2GSR - address 0xE004 8008) bit

description

Bit Symbol Value Function Reset

Value RM

Set