UM10237_2 © NXP B.V. 2008. All rights reserved.
User manual Rev. 02 — 19 December 2008 58 of 792
NXP Semiconductors UM10237
Chapter 4: LPC24XX Clocking and power control
3.3.4 Peripheral Clock Selection registers 0 and 1 (PCLKSEL0 - 0xE01F C1A8 and PCLKSEL1 - 0xE01F C1AC)

A pair of bits in a Peripheral Clock Selection register controls the rate of the clock signal

that will be supplied to the corresponding peripheral as specified in Table4–56,

Table4–57 and Table 4–58.

[1] For PCLK_RTC only, the value ’01’ is illegal. Do not write ’01’ to the PCLK_RTC. Attempting to write ’01’
results in the previous value being unchanged.
Table 55. IRC Trim register (IRCTRIM - address 0xE01F C1A4) bit description
Bit Symbol Description Reset
value
7:0 IRCtrim IRC trim value. It controls the on-chip 4 MHz IRC frequency. 0xA0
15:8 - Reserved. Software must write 0 into these bits. NA
Table 56. Peripheral Clock Selection register 0 (PCLKSEL0 - address 0xE01F C1A8) bit
description
Bit Symbol Description Reset
value
1:0 PCLK_WDT Peripheral clock selection for WDT. 00
3:2 PCLK_TIMER0 Peripheral clock selection for TIMER0. 00
5:4 PCLK_TIMER1 Peripheral clock selection for TIMER1. 00
7:6 PCLK_UART0 Peripheral clock selection for UART0. 00
9:8 PCLK_UART1 Peripheral clock selection for UART1. 00
11:10 PCLK_PWM0 Peripheral clock selection for PWM0. 00
13:12 PCLK_PWM1 Peripheral clock selection for PWM1. 00
15:14 PCLK_I2C0 Peripheral clock selection for I2C0. 00
17:16 PCLK_SPI Peripheral clock selection for SPI. 00
19:18 PCLK_RTC[1] Peripheral clock selection for RTC. 00
21:20 PCLK_SSP1 Peripheral clock selection for SSP1. 00
23:22 PCLK_DAC Peripheral clock selection for DAC. 00
25:24 PCLK_ADC Peripheral clock selection for ADC. 00
27:26 PCLK_CAN1 Peripheral clock selection for CAN1. 00
29:28 PCLK_CAN2 Peripheral clock selection for CAN2. 00
31:30 PCLK_ACF Peripheral clock selection for CAN filtering. 00
Table 57. Peripheral Clock Selection register 1 (PCLKSEL1 - address 0xE01F C1AC) bit
description
Bit Symbol Description Reset
value
1:0 PCLK_BAT_RAM Peripheral clock selection for the battery supported RAM. 00
3:2 PCLK_GPIO Peripheral clock selection for GPIOs. 00
5:4 PCLK_PCB Peripheral clock selection for the Pin Connect block. 00
7:6 PCLK_I2C1 Peripheral clock selection for I2C1. 00
9:8 - Unused, always read as 0. 00
11:10 PCLK_SSP0 Peripheral clock selection for SSP0. 00