NXP Semiconductors UM10237 - page 287

UM10237_2 © NXP B.V. 2008. All rights reserved.
User manual Rev. 02 — 19 December 2008 287 o f 792
NXP Semiconductors UM10237
Chapter 12: LPC24XX LCD controller
6.1.2 AMBA AHB master interface
The AHB master interface transfers display data from a selected slave (memory) to the
LCD controller DMA FIFOs. It can be configured to obtain data from the 16 kB, on-chip
SRAM on AHB1, various types of off-chip static memory, or off-chip SDRAM.
In dual panel mode, the DMA FIFOs are filled up in an alternating fashion via a single
DMA request. In single panel mode, the DMA FIFOs are filled up in a sequential fashion
from a single DMA request.
The inherent AHB master interface state machine performs the following functions:
•Loads the upper panel base address into the AHB address incrementer on
recognition of a new frame.
•Monitors both the upper and lower DMA FIFO levels and asserts a DMA request to
request display data from memory, filling them to above the programmed watermark.
the DMA request is reasserted when there are at least four locations available in
either FIFO (dual panel mode).
•Checks for 1KB boundaries during fixed-length bursts, appropriately adjusting the
address in such occurrences.
•Generates the address sequences for fixed-length and undefined bursts.
•Controls the handshaking between the memory and DMA FIFOs. It inserts busy
cycles if the FIFOs have not completed their synchronization and updating sequence.
•Fills up the DMA FIFOs, in dual panel mode, in an alternating fashion from a single
DMA request.
•Asserts the a bus error interrupt if an error occurs during an active burst.
•Responds to retry commands by restarting the failed access. This introduces some
busy cycles while it re-synchronizes.
6.2 Dual DMA FIFOs and associated control logic
The pixel data accessed from memory is buffered by two DMA FIFOs that can be
independently controlled to cover single and dual-panel LCD types. Each FIFO is 16
words deep by 64 bits wide and can be cascaded to form an effective 32-Dword deep
FIFO in single panel mode.
Synchronization logic transfers the pixel data from the AHB clock domain to the LCD
controller clock domain. The water level marks in each FIFO are set such that each FIFO
requests data when at least four locations become available.
An interrupt signal is asserted if an attempt is made to read either of the two DMA FIFOs
when they are empty (an underflow condition has occurred).
6.3 Pixel serializer
This block reads the 32-bit wide LCD data from the output port of the DMA FIFO and
extracts 24, 16, 8, 4, 2, or 1 bpp data, depending on the current mode of operation. The
LCD controller supports big-endian, little-endian, and Windows CE data formats.
Depending on the mode of operation, the extracted data can be used to point to a color or
gray scale value in the palette RAM or can actually be a true color value that can be
directly applied to an LCD panel input.