NXP Semiconductors UM10237

User manual Rev. 02 — 19 December 2008 763 o f 792

Chapter 36: LPC24XX Supplementary information

Interrupt Controller . . . . . . . . . . . . . . . . . . . . .115

Table 117.Interrupt sources bit allocation table. . . . . . . . 117

Table 118.LPC2400 pin configurations overview . . . . . .119

Table 119.LPC2458 pin allocation table . . . . . . . . . . . . .120

Table 120.Pin description . . . . . . . . . . . . . . . . . . . . . . . .123

Table 121.LPC2420/60/68 pin allocation table . . . . . . . .136

Table 122.LPC2420/60/68 pin description . . . . . . . . . . .139

Table 123.LPC2470/78 pin allocation table . . . . . . . . . .154

Table 124.LPC2470/78 pin description . . . . . . . . . . . . .157

Table 125.Boot control on pins P3[15]/D15 and

P3/14]/D14 . . . . . . . . . . . . . . . . . . . . . . . . . . .174

Table 126.LPC2400 PINSEL register use. . . . . . . . . . . . 176

Table 127.Pin function select register bits. . . . . . . . . . . .177

Table 128.Pin Mode Select register bits . . . . . . . . . . . . .177

Table 129.Summary of pin connect block registers. . . . .177

Table 130.Pin function select register 0 (PINSEL0 - address

0xE002 C000) bit description. . . . . . . . . . . . .178

Table 131.Pin function select register 1 (PINSEL1 - address

0xE002 C004) bit description. . . . . . . . . . . . .179

Table 132.Pin function select register 2 (PINSEL2 - address

0xE002 C008) bit description. . . . . . . . . . . . .180

Table 133.Pin function select register 3 (PINSEL3 - address

0xE002 C00C) bit description. . . . . . . . . . . . .181

Table 134.LPC2458 pin function select register 4 (PINSEL4

- address 0xE002 C010) bit description . . . . .182

Table 135.LPC2420/60/68/70/78 pin function select register

4 (PINSEL4 - address 0xE002 C010) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . .182

Table 136.LPC2458 pin function select register 5 (PINSEL5

- address 0xE002 C014) bit description . . . . .184

Table 137.LPC2420/60/68/70/78 pin function select register

5 (PINSEL5 - address 0xE002 C014) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . .184

Table 138.Pin function select register 6 (PINSEL6 - address

0xE002 C018) bit description. . . . . . . . . . . . .185

Table 139.LPC2458 pin function select register 7 (PINSEL7

- address 0xE002 C01C) bit description. . . . .185

Table 140.LPC24520/60/68/70/78 pin function select

description . . . . . . . . . . . . . . . . . . . . . . . . . . .186

Table 141.Pin function select register 8 (PINSEL8 - address

0xE002 C020) bit description. . . . . . . . . . . . .187

Table 142.LPC2458 pin function select register 9 (PINSEL9

- address 0xE002 C024) bit description . . . . .187

Table 143.LPC2420/60/68/70/78 pin function select register

9 (PINSEL9 - address 0xE002 C024) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . .188

Table 144.Pin function select register 10 (PINSEL10 -

address 0xE002 C028) bit description . . . . . .189

Table 145.Pin function select register 11 (PINSEL11 -

address 0xE002 C02C) bit description. . . . . . 189

Table 146.Pin Mode select register 0 (PINMODE0 - address

0xE002 C040) bit description. . . . . . . . . . . . .189

Table 147.Pin Mode select register 1 (PINMODE1 - address

0xE002 C044) bit description. . . . . . . . . . . . .190

Table 148.Pin Mode select register 2 (PINMODE2 - address

0xE002 C048) bit description. . . . . . . . . . . . .190

Table 149.Pin Mode select register 3 (PINMODE3 - address

0xE002 C04C) bit description . . . . . . . . . . . . 190

Table 150.Pin Mode select register 4 (PINMODE4 - address

0xE002 C050) bit description. . . . . . . . . . . . .191

Table 151.Pin Mode select register 5 (

PINMODE5 -

address 0xE002 C054) bit description. . . . . . 191

Table 152.Pin Mode select register 6 (PINMODE6 - address

0xE002 C058) bit description. . . . . . . . . . . . .191

Table 153.Pin Mode select register 7 (PINMODE7 - address

0xE002 C05C) bit description . . . . . . . . . . . . 191

Table 154.Pin Mode select register 8 (PINMODE8 - address

0xE002 C060) bit description. . . . . . . . . . . . .192

Table 155.Pin Mode select register 9 (PINMODE9 - address

0xE002 C064) bit description. . . . . . . . . . . . .192

Table 156.LPC2400 available port pins . . . . . . . . . . . . . 193

Table 157.GPIO pin description . . . . . . . . . . . . . . . . . . .195

Table 158.Summary of GPIO registers (legacy APB

accessible registers) . . . . . . . . . . . . . . . . . . . 196

Table 159.Summary of GPIO registers (local bus accessible

registers - enhanced GPIO features). . . . . . .197

Table 160.GPIO interrupt register map. . . . . . . . . . . . . .198

Table 161.GPIO port Direction register (IO0DIR - address

0xE002 8008 and IO1DIR - address

0xE002 8018) bit description. . . . . . . . . . . . . 198

Table 162.Fast GPIO port Direction register

(FIO[0/1/2/3/4]DIR - address

0x3FFF C0[0/2/4/6/8]0) bit description. . . . . .198

Table 163.Fast GPIO port Direction control byte and

half-word accessible register description. . . . 199

Table 164.GPIO port output Set register (IO0SET - address

0xE002 8004 and IO1SET - address

0xE002 8014) bit description. . . . . . . . . . . . . 200

Table 165.Fast GPIO port output Set register

(FIO[0/1/2/3/4]SET - address

0x3FFF C0[1/3/5/7/9]8) bit description. . . . . .200

Table 166.Fast GPIO port output Set byte and half-word

accessible register description. . . . . . . . . . . . 200

Table 167.GPIO port output Clear register (IO0CLR -

address 0xE002 800C and IO1CLR - address

0xE002 801C) bit description. . . . . . . . . . . . .201

Table 168.Fast GPIO port output Clear register

(FIO[0/1/2/3/4]CLR - address

0x3FFF C0[1/3/5/7/9]C) bit description . . . . . 201

Table 169.Fast GPIO port output Clear byte and half-word

accessible register description. . . . . . . . . . . . 202

Table 170.GPIO port Pin value register (IO0PIN - address

0xE002 8000 and IO1PIN - address

0xE002 8010) bit description. . . . . . . . . . . . . 203

Table 171.Fast GPIO port Pin value register

(FIO[0/1/2/3/4]PIN - address

0x3FFF C0[1/3/5/7/9]4) bit description. . . . . .203

Table 172.Fast GPIO port Pin value byte and half-word

accessible register description. . . . . . . . . . . . 204

Table 173.Fast GPIO port Mask register

(FIO[0/1/2/3/4]MASK - address

0x3FFF C0[1/3/5/7/9]0) bit description. . . . . .205

Table 174.Fast GPIO port Mask byte and half-word

accessible register description. . . . . . . . . . . . 205