UM10237_2 © NXP B.V. 2008. All rights reserved.
User manual Rev. 02 — 19 December 2008 639 o f 792
NXP Semiconductors UM10237
Chapter 25: LPC24XX Pulse Width Modulator PWM0/PWM1
[1] Reset Value relects the data stored in used bits only. It does not include reserved bits content.
6.1 PWM Interrupt Register (PWM0IR - 0xE001 4000 and PWM1IR 0xE001 8000)

The PWM Interrupt register consists of eleven bits (Table25–558), seven for the match

interrupts and four reserved. If an interrupt is generated then the corresponding bit in the

PWMIR will be high. Otherwise, the bit will be low. Writing a logic one to the corresponding

IR bit will reset the interrupt. Writing a zero has no effect.

MR4 Match Register 4. MR4 can be enabled in the MCR to
reset the TC, stop both the TC and PC, and/or generate
an interrupt when it matches the TC. In addition, a match
between this value and the TC clears PWM4 in either
edge mode, and sets PWM5 if it’s in double-edge mode.
R/W 0 0xE0014040
PWM0MR 0xE001 8040
PWM1MR
MR5 Match Register 5. MR5 can be enabled in the MCR to
reset the TC, stop both the TC and PC, and/or generate
an interrupt when it matches the TC. In addition, a match
between this value and the TC clears PWM5 in either
edge mode, and sets PWM6 if it’s in double-edge mode.
R/W 0 0xE0014044
PWM0MR 0xE001 8044
PWM1MR
MR6 Match Register 6. MR6 can be enabled in the MCR to
reset the TC, stop both the TC and PC, and/or generate
an interrupt when it matches the TC. In addition, a match
between this value and the TC clears PWM6 in either
edge mode.
R/W 0 0xE0014048
PWM0MR 0xE001 8048
PWM1MR
PCR PWM Control Register. Enables PWM outputs and
selects PWM channel types as either single edge or
double edge controlled.
R/W 0 0xE001404C
PWM0PCR 0xE001 804C
PWM1PCR
LER Load Enabl e Register. Enables use of new PWM match
values. R/W 0 0xE0014050
PWM0LER 0xE001 8050
PWM1LER
CTCR Count Control Register. The CTCR selects between
Timer and Counter mode, and in Counter mode selects
the signal and edge(s) for counting.
R/W 0 0xE0014070
PWM0CTCR 0xE001 8070
PWM1CTCR
Table 557. PWM0 and PWM1 register map
Generic
Name Description Access Reset
Value[1] PW M0 Address
& Name PWM1 Address
& Name
Table 558: PWM Interrupt Register (PWM0IR - address 0xE001 4000 and PWM1IR address
0xE001 8000) bit description
Bit Symbol Description Reset
Value
0 PWMMR0 Interrupt Interrupt flag for PWM match channel 0. 0
1 PWMMR1 Interrupt Interrupt flag for PWM match channel 1. 0
2 PWMMR2 Interrupt Interrupt flag for PWM match channel 2. 0
3 PWMMR3 Interrupt Interrupt flag for PWM match channel 3. 0
4PWMCAP0
Interrupt Interrupt flag for capture input 0 0
5PWMCAP1
Interrupt Interrupt flag for capture input 1 (available in PWM1IR only;
this bit is reserved in PWM0IR). 0
7:6 - Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined. -
8 PWMMR4 Interrupt Interrupt flag for PWM match channel 4. 0