ADC
The HP 8560A uses a successive-approximation type of ADC. The ADC Algorithmic State Machine (ADC ASM) controls the interface between the Start/Stop Control and the ADC itself, switching between positive and negative peak detectors when the NORMAL detector mode is selected, and switching the Ramp Counter into the ADC for comparison to the analog sweep ramp.
Log Expand/Video Functions (P/O A3)
The A3 Interface assembly performs log expand and offset functions. The Log Expand/Log Offset Amplifier provides a 2 dB/Div log scale. The 5 dB/Div scale is derived by multiplying the digitized 10 dB/Div trace data by two in the CPU. The 1 dB/Div scale is similarly derived by multiplying the 2 dB/Div trace data by two.
The analyzer uses two types of video filters. An RC low-pass circuit provides 300 Hz to 3 MHz video bandwidths. Video bandwidths of 1 Hz to 100 Hz are filtered digitally by the CPU. When a digital filter is selected, a D appears along the left edge of the CRT, indicating that something other than the normal detector mode is being used. Digitally filtered bandwidths use a sample detector.
After filtering, the video is sent to the Positive and Negative Peak Detectors. These detectors are designed for optimum pulse response. The Positive Peak Detector resets at the end of each horizontal “bucket” (there are 601 such buckets across the screen). The Negative Peak Detector resets at the end of every other bucket. When reset, the output of the peak detector equals its input.
Triggering
The HP 8560A has five trigger modes: free run, single, external, video, and line. The Free Run and Single trigger signal comes from the 1 MHz ADC clock. The line trigger signal comes from the A6 Power Supply. Video triggering originates from A3’s video filter buffer circuit. External triggering requires a TTL logic high level received from a rear-panel BNC connector. A DAC in the trigger circuit sets the video trigger level. The trigger circuit is responsible for setting HSCAN high.
,Controller Section
The Controller Section includes the A2 Controller Assembly and A19 HP-IB Assembly. The A2 assembly controls the A4 Cal Oscillator and Al7 CRT driver through W7. The battery on the rear panel provides battery-backup for STATE and TRACE storage.
The A2 contains the CPU, RAM, ROM, the Display ASM and Line Generators, CRT blanking, focus, intensity control, HP-IB Interface, Frequency Counter, Display RAM, Option Module interface, and EEROM. The A19 HP-IB is a mechanical interface between the standard HP-IB connector and the ribbon cable connector on the A2 Controller Assembly.
All four RAM IC’s are battery-backed. The battery-backed RAM stores trace information (two Display Memory RAMS) and analyzer state information (two program RAMS). A total of eight traces and ten states may be stored. Typical battery life is five years with the lithium battery. Trace and state information may be retained for up to 30 minutes with a dead battery and power turned off. This is due to the RAM’s very low data retention current.
