A3 Assembly’s ADC CircuitsThe ADC consists of a 12-bit DAC, 12-bit successive approximation register (SAR), data multiplexers, and data latches. The ADC ASM (algorithmic state machine) controls the ADC. Eight inputs are controlled by the ADC MUX. These include a positive peak detector, negative peak detector, sampled video, scan ramp, YTO error voltage, FC MUX voltages, Cal Oscillator tune voltage, and offset lock error voltage. A MUX on the Al4 Frequency Control Assembly selects which voltage is sent to the ADC MUX on the FC MUX signal line.
During NORMAL detector mode sweeps, when noise is detected by the rosenfell detector, the ADC ASM automatically switches between POS PEAK and NEG PEAK.
ADC Control Signals
See function blocks B and F of A3 Interface Assembly Schematic Diagram (sheet 2 of 6).
The ADC requires two signals from the A2 Controller Assembly: HBADC-CLKO and HBBKT-PULSE. HBBKT-PULSE is used only in zero span. Use the following steps to verify the signals.
1.Disconnect W22 from A2J8.
2.If a 10 MHz TTL signal is absent on W22, refer to the 10 MHz Reference (on the Al5 RF Assembly) troubleshooting procedure in Chapter 11.
3.Set the HP 8560A’s ISPAN) to zero.
4.Reconnect W22.
5.With an oscilloscope probe, monitor A3J401 pin 20.
6.If TTL pulses are absent, the A2 Controller Assembly is faulty. Refer to Chapter 9. The presence of TTL pulses indicates a faulty A3 assembly.
7.Monitor A3J401 pin 23 (HBADC-CLKO). If a 1 MHz TTL clock signal is present, HBADC-CLKO is working properly.
8.If HBKT-PULSE or HBADC-CLKO is missing, disconnect A3Wl from A2J2.
9.Monitor A2U5 pin 3 for HBKT-PULSE and A2U5 pin 7 for HBADC-CLKO.
10.If HBADC-CLKO is absent, troubleshoot the A2 Controller assembly.
11.HBKT-PULSE is absent, refer to the information on troubleshooting the frequency counter in Chapter 9.
12. Reconnect A3Wl to A2J2.
