Table 7-5. Counter Frequencies

 

 

 

 

 

A3U606 pin #

 

Nominal Frequency (Hz)

 

 

 

 

 

3

 

3900

 

4

 

1950

 

5

 

975

 

6

 

488

 

11

 

244

 

10

 

122

 

 

 

 

 

 

 

 

Triggering Problems

See function block H of A3 Interface Assembly Schematic Diagram (sheet 3 of 6).

The 1 MHz ADC clock provides synchronization in FREE RUN and SINGLE triggering. LINE triggering synchronization originates on the A6 Power Supply. Trigger MUX A3U613A selects between FREE RUN, VIDEO, LINE, and EXTERNAL trigger sources. The trigger signal sets the output of the HSCAN latch high. HBADC-CLKO provides the trigger

signal for FREE RUN. The VIDEO TRIG signal must be at least 25 mV (0.25 divisions) peak-to-peak to trigger in video trigger mode.

1.Check that the trigger MUX is receiving the proper trigger source information by selecting each of the following trigger modes and checking the TRIG-SOURCE0 and TRIG-SOURCE1 lines as indicated in Table 7-6 below.

2.If a trigger mode does not work, check that a trigger signal is present at the appropriate MUX input, as indicated in Table 7-6.

Table 7-6. Trigger MUX Truth Table

Trigger Mode

TRIG-SOURCE0

TRIG-SOURCE1

MUX Input

 

U613 pin 14

U613 pin 2

Pin Number U613

FREE RUN

L

L

6

VIDEO

H

L

5

LINE

H

H

3

EXTERNAL

L

H

4

3.Check that the appropriate MUX input signal is present at the MUX output (A3U613 pin 7).

4.To check the video trigger level DAC, connect a DVM’s positive lead to A3J400 pin 1 and the negative DVM lead to A3TP4.

5.Press ITRIG) and VIDEO.

6.Press the STEP @ key several times while noting the DVM reading and position of the video trigger level on the screen.

7.Check that the voltage displayed on the DVM increases by 1 V for each step of the VIDEO TRIG LEVEL.

ADC/lnterface Section 7-9