Digi NS9215 manuals

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Digi NS9215 Manual

Digi NS9215 Manual

517 pages2.22 Mb

5Contents
27Pinout (265)
T
- 28Memory bus interface
- 30Ethernet interface MAC
- 31General purpose I/O (GPIO)
- 43System clock
- 45System mode
- 47System reset
  - POR
  - NS9215 Core
  - NS9215
- 48JTAG Test
- 49ADC
  - If the ADC feature is not used, the inputs must be terminated as shown below:
- 50POR and battery-backed logic
  - If the RTC feature is not used, the inputs must be terminated as shown below.
  - If the RTC feature is used, see RTC clock and battery backup drawing on page45.
- 51Power and ground
53I/O Control Module
T
- Control and Status registers
- 55GPIO Configuration registers
- 70GPIO Control registers
- 74GPIO Status registers
  - 75GPIO Status Register #2 Address: A090_2084
  - GPIO Status Register #3 Address: A090_2088
- 76Memory Bus Configuration register
Working with the CPU
81T
- 82Instruction sets
- 83System control processor (CP15) registers
- 86R0: ID code and cache type status registers
- 88R1: Control register
  - the BIGENDINIT signal is high.
  - All defined control bits are set to zero on reset except the V bit and B bit.
  - 89Control register
  - Bit functionality
- 91R2: Translation Table Base register
- R3:Domain Access Control register
- 92R4 register
- R5: Fault Status registers
- 93R6: Fault Address register
- 94R7:Cache Operations register
  - Cache functions This table describes the cache functions provided by register R7.
- 97R8:TLB Operations register
- 98R9: Cache Lockdown register
- 101R10:TLB Lockdown register
- 102R11 and R12 registers
- R13:Process ID register
- 104R14 register
- R15: Test and debug register
- Jazelle(Java)
- 105DSP
- MemoryManagement Unit (MMU)
  - 109Tabl e wa lk process
  - 117Translating sequence for small page references
- 119MMU faults and CPU aborts
- 121Domain access control
- 122Fault checking sequence
  - 123Fault checking sequence
- 125External aborts
- Enabling and disabling the MMU
- 126TLB structure
- 127Caches and write buffer
- 130Cache MVA and Set/Way formats
  - Cache MVA and Set/Way formats
  - 131Generic, virtually indexed, virtually addressed cache
- 133Noncachable instruction fetches
- System Control Module
137T
- Bus interconnection
- 138System bus arbiter
- 141Address decoding
- 142Programmable timers
- 143General purpose timers/counters
- 144Basic PWM function
- 145Enhanced PWM function
- Quadrature decoder function
- 146How the quadrature decoder/counter works
  - 00 01 101100 01 1011 00 00 1001 01 0011 Clockwi se Counter Clockwise
  - 147Motor Encoder Quadrature Decoder/ Counter
  - ControllerA Host
- 148Interrupt controller
  - 150The interrupt sources are assigned as shown:
- 151Vectored interrupt controller (VIC) flow
- Configurable system attributes
- PLL configuration
  - Bootstrap initialization
  - PLL configuration and control system block diagram
- 152Bootstrap initialization
  - 0 = Use an external pulldown 1 = Use the internal pullup
  - Sample Clock Frequency Settings With 29.4912MHz Crystal (NF+1 = 61 and OD + 1 = 1)
    - Restrictions RefClk / NR+1 range: 275KHz 550MHz PLL Vco range: 110MHz 550MHz
- 154System configuration registers
  - All configuration registers must be accessed as 32-bit words and as single accesses
  - Register address map
- 158General Arbiter Control register
- BRC0, BRC1, BRC2, and BRC3 registers
  - Channel allocation This is how the channels are assigned in the four registers:
  - Address: A090 0018
- 159AHB Error Detect Status 1
- 160AHB Error Detect Status 2
  - Register bit
- 161AHB Error Monitoring Configuration register
  - Register bit
- 162Timer Master Control register
- 164Timer 04 Control registers
  - Addresses: A090 0190 / 0194 / 0198 / 019C / 01A0
- 166Timer 5 Control register
  - Address: A090 01A4
- 168Timer 69 Control registers
  - Addresses: A090 01A8 / 01AC / 01B0 / 01B4
- 170Timer 69 High registers
- 171Timer 69 Low registers
- 172Timer 69 High and Low Step registers
- Timer 69 Reload Step registers
- 173Timer 0-9 Reload Count and Compare register
- 174Timer 0-9 Read and Capture register
- 175Interrupt Vector Address Register Level 310
- Int (Interrupt) Config (Configuration) 310 registers
- 176ISADDR register
- 177Interrupt Status Active
- 178Interrupt Status Raw
- Software Watchdog Configuration
  - Register bit
- 179Software Watchdog Timer
  - Address: A090 0178 The Software Watchdog Timer register services the watchdog timer.
    - Clock Configuration register
  - Register bit
- 180Clock Configuration register
  - D31:00 R/W Watchdog timer 0x0 Watchdog timer
  - the watchdog timer, but will not change the contents.
  - based on the write data value.
- 182Module Reset register
  - Address: A090 0180
  - 183The Module Reset register resets each module on the AHB bus.
  - Register bit
- 184Miscellaneous System Configuration and Status register
- 186PLL Configuration register
  - Active Interrupt Level ID Status register
- 187Active Interrupt Level ID Status register
  - Register bit
- Power Management
  - Address: A090 0228 The power management register controls the processor power management features.
- 190AHB Bus Activity Status
- System Memory Chip Select 0 Dynamic Memory Base and
- 191System Memory Chip Select 1 Dynamic Memory Base and
- 192System Memory Chip Select 2 Dynamic Memory Base and
- 193System Memory Chip Select 3 Dynamic Memory Base and
- 194System Memory Chip Select 0 Static Memory Base and Mask
- 195System Memory Chip Select 1 Static Memory Base and Mask
- 196System Memory Chip Select 2 Static Memory Base and Mask
- 197System Memory Chip Select 3 Static Memory Base and Mask
- 198Gen ID register
- 199External Interrupt 03 Control register
- 200RTC Module Control register
  - Address: A090 0224 The RTC Module Control register controls the RTC module.
  - Register bit
- Memory Controller
203T
- 204Low-power operation
- 205Memory map
- 207Static memory controller
- 209Static memory initialization
- 210Static memory read control
- 211Static memory read: Timing and parameters
- 214Asynchronous page mode read
- Asynchronous page mode read: Timing and parameters
- 216Static memory write control
- Static memory Write: Timing and parameters
- 219Bus turnaround
- Bus turnaround: Timing and parameters
- 221Byte lane control
- 222Address connectivity
  - Address connectivity
  - 223Memory banks constructed from 16-or 32-bit memory devices
  - Memory bank constructed from 32-bit memory
  - MEMORY CONTROLLER
  - 224Address connectivity
- 225Dynamic memory controller
- SDRAM Initialization
  - Left-shift value table: 16-bit wide data bus SDRAM (BRC)
- 228SDRAM address and data bus interconnect
  - 22932-bit wide configuration
  - 230Register map All configuration registers must be accessed as 32-bit words and as single accesses
- 232Control register
  - 233Register bit assignment
- 234Status register
- Configuration register
  - Register bit
- 235Dynamic Memory Control register
  - Register bit
- 236Dynamic Memory Refresh Timer register
  - Address: A070 0024
- 237Dynamic Memory Read Configuration register
- 238Dynamic Memory Precharge Command Period register
- 239Dynamic Memory Active to Precharge Command Period
- register
- 240Dynamic Memory Self-refresh Exit Time register
- Dynamic Memory Last Data Out to Active Time register
- 241Dynamic Memory Data-in to Active Command Time register
- 242Dynamic Memory Write Recovery Time register
- 243Dynamic Memory Active to Active Command Period register
- Dynamic Memory Auto Refresh Period register
- 244Dynamic Memory Exit Self-refresh register
- 245Dynamic Memory Active Bank A to Active Bank B Time
- register
- 246Dynamic Memory Load Mode register to Active Command
- Time register
- 247Static Memory Extended Wait register
- Dynamic Memory Configuration 03 registers
  - 248Register bit
  - 249Address mapping for the Dynamic Memory Configuration registers
- 250Dynamic Memory RAS and CAS Delay 03 registers
  - Address: A070 0104 / 0124 / 0144 / 0164
- 251StaticMemory Configuration 03 registers
- 254StaticMemory Write Enable Delay 03 registers
- 255Static Memory Output Enable Delay 03 registers
- 256Static Memory Read Delay 03 registers
- StaticMemory Page Mode Read Delay 03 registers
- 257Static Memory Write Delay 03 registers
- 258StaticMemory Turn Round Delay 03 registers
- Ethernet Communication Module
261T
- 262Ethernet MAC
  - 263MAC module block diagram
  - MAC module features
- 264Station address logic (SAL)
- 265Statistics module
  - ETHERNET COMMUNICATION MODULE
  - Ethernet front-end module
- 266Ethernet front-end module
  - Ethernet front- end module (EFE)
- 267Receive packet processor
  - Receive buffer descriptor field definitions
- 269Transmit packet processor
- 273Ethernet slave interface
- Interrupts
- 274Resets
- 275Multicast address filtering
- 276Clock synchronization
- 277Ethernet Control and Status registers
  - All configuration registers must be accessed as 32-bit words and as single accesses
  - Register address filter
- 279Ethernet General Control Register #1
  - Address: A060 0000
- 282Ethernet General Control Register #2
  - Address: A060 0004
  - Register bit
- 283Ethernet General Status register
  - Address: A060 0008
    - ETHERNET COMMUNICATION MODULE
    - Ethernet Transmit Status register
  - Register bit
- 284Ethernet Transmit Status register
  - 285Register bit assignment
- 286Ethernet Receive Status register
- 288MAC Configuration Register #1
  - Register bit
- 289MAC Configuration Register #2
  - Register bit
- 291Back-to-Back Inter-Packet-Gap register
  - Register bit
- 292Non Back-to-Back Inter-Packet-Gap register
  - Address: A060 040C
  - Register bit assignment
- 293Collision Window/Retry register
  - Address: A060 0410
  - Register bit
- 294Maximum Frame register
  - Address: A060 0414
  - Register bit
- 295MII Management Configuration register
  - Address: A060 0420
  - Register bit
  - Clocks field settings
- 296MII Management Command register
  - Address: A060 0424
  - Register bit
  - If both SCAN and READ are set, SCAN takes precedence.
- 297MII Management Address register
  - Address: A060 0428
  - Register bit
- 298MII Management Write Data register
  - Address: A060 0430
  - Address: A060 042C
  - Register bit
- MII Management Read Data register
- 299MII Management Indicators register
- 300Station Address registers
- 301Station Address Filter register
- 302RegisterHash Tables
- 303Statistics registers
  - 311Register bit
  - Carry Register 2 Address: A060 0734
  - 312Register bit
  - Carry Register 1 Mask register Address: A060 0738
  - 314Carry Register 2 Mask register Address: A060 073C
  - Register bit
- 315RX_A Buffer Descriptor Pointer register
- RX_B Buffer Descriptor Pointer register
- 316RX_C Buffer Descriptor Pointer register
- RX_D Buffer Descriptor Pointer register
- 317Ethernet Interrupt Status register
- 319Ethernet Interrupt Enable register
  - Register bit
- 320TX Buffer Descriptor Pointer register
  - Address: A060 0A18
  - Register bit
- 321Transmit Recover Buffer Descriptor Pointer register
  - Address: A060 0A1C
  - Register bit
- TX Error Buffer Descriptor Pointer register
  - Address: A060 0A20
  - Register bit
- 322TX Stall Buffer Descriptor Pointer register
  - Address: A060 0A24
  - Register bit
- 323RX_A Buffer Descriptor Pointer Offset register
  - Address: A060 0A28
  - Register bit
- 324RX_B Buffer Descriptor Pointer Offset register
- RX_C Buffer Descriptor Pointer Offset register
- 325RX_D Buffer Descriptor Pointer Offset register
- Transmit Buffer Descriptor Pointer Offset register
- 326RX Free Buffer register
- 327Multicast Address Filter registers
- 329Multicast Address Mask registers
- 331Multicast Address Filter Enable register
  - Register bit
- 332TX Buffer Descriptor RAM
- 333RX FIFO RAM
- 334Sample hash table code
- 339External DMA
- T
- 355AES Data Encryption/Decryption Module
- T
  - Block diagram
  - 356AES DMA buffer descriptor
  - 359Decryption
  - ECB processing
    - AES DATA ENCRYPTION/DECRYPTION MODULE
    - CBC, CFB, OFB, and CTR processing
  - 360CBC, CFB, OFB, and CTR processing
  - CCM mode
    - CCM mode does not require an initialization vector.
      - AES DATA ENCRYPTION/DECRYPTION MODULE
      - 361CCM mode
        www.digiembedded.com
    - Bits 127:120 119:8*L-par 8*L-par-1:0 Contents reserved Nonce Message length
  - 364DMA controller
  - 367Transmit DMA example
  - 368Control and status register address maps
    - 369Registers 9000_0000 9000_7FFF and registers 9000_8000 9000_FFFF are reserved. UART A register
    - UART B register
    - 370UART C register
    - UART D register
  - 372[Module] Interrupt and FIFO Status register
  - 375[Module] DMA RX Control
  - 376[Module] DMA RX Buffer Descriptor Pointer
  - 377[Module] RX Interrupt Configuration register
  - 378[Module] Direct Mode RX Status FIFO
  - 379[Module] Direct Mode RX Data FIFO
  - 380[Module] DMA TX Control
    - Register bit
  - 381[Module] DMA TX Buffer Descriptor Pointer
  - [Module] TX Interrupt Configuration register
  - 382[Module] Direct Mode TX Data FIFO
  - 383[Module] Direct Mode TX Data Last FIFO
- Serial Control Module: UART
385T
- UART module structure
- 386Normal mode operation
  - IO Hub
  - Receive FIFO Interface
  - Transmit FIFO Interface
  - UART
- 387Baud rate generator
  - BR = CLKref / (BRD x 16)
- 388Hardware-based flow control
- Character-based flow control (XON/XOFF)
- Forced character transmission
- 389ARM wakeup on character recognition
- 390Wrapper Control and Status registers
- 391Wrapper Configuration register
  - Register bit
  - 393Register bit
- 398Receive Character GAP Control register
- 399Receive Buffer GAP Control register
- Receive Character Match Control register
- 400Receive Character-Based Flow Control register
  - 401Caution:
  - Be aware that if multiple matches occur, an XOFF assertion will supersede an XON assertion.
- 402Force Transmit Character Control register
  - Register bit
- 403ARM Wakeup Control register
- 404Transmit Byte Count
- 405UART Receive Buffer
- UART Transmit Buffer
- 406UART Baud Rate Divisor LSB
- UART Baud Rate Divisor MSB
- 407UART Interrupt Enable register
- 408UART Interrupt Identification register
- 409UART FIFO Control register
- UART Line Control register
- 411UART Modem Control register
- UART Line Status register
- 412UART Modem Status register
- Serial Control Module: HDLC
415T
- Receive and transmit operations
- 416Clocking
- Bits
- 417Data encoding
- 418Digital phase-locked-loop (DPLL) operation: Encoding
- 419DPLL operation: Adjustment ranges and output clocks
- 421Normal mode operation
- 422Wrapper and HDLC Control and Status registers
- Wrapper Configuration register
  - 424Register bit
- 427HDLC Data Register 1
- HDLC Data Register 2
- 428HDLC Data register 3
- 429HDLC Control Register 1
- HDLC Control Register 2
  - Register bit
- 430HDLC Clock Divider Low
  - Address: 9002_9118
- 431HDLC Clock Divider High
- Serial Control Module: SPI
433T
- 434SPI controller
- 435SPI clocking modes
- 436SPI clock generation
- System boot-over-SPI operation
  - 437Avail able strapping options
- 439SPI Control and Status registers
- SPI Configuration register
- 440Clock Generation register
  - Address: 9003_1010
  - Register bit
- 443SPI timing characteristics
- I2C Master/Slave Interface
447T
- Physical I2C bus
- 448I2C external addresses
- 449I2C command interface
- 450I2C registers
- Command Transmit Data register
- 451Status Receive Data register
- 452Master Address register
  - Register bit
- 453Slave Address register
  - Register bit
- 454Configuration register
- 455Interrupt Codes
  - Master/slave interrupt codes
- 456Software driver
  - I2C MASTER/SLAVE INTERFACE
  - Flow charts
    - www.digiembedded.com
- 457Flow charts
  - Master module (normal mode, 16- bit)
    - Notes:
    - I2C MASTER/SLAVE INTERFACE
    - Flow charts
  - 458Slave module (normal mode, 16- bit)
    - Note:
- Real Time Clock Module
459T
- 460RTC configuration and status registers
- RTC General Control register
- 46112/24 Hour register
- 462Time register
- 463Calendar register
- 464Time Alarm register
  - Address: 9006 0010 The Time Alarm register sets the time alarm. BCD is binary coded decimal.
  - Register bit
- 465Calendar Alarm register
- Alarm Enable register
- 466Event Flags register
  - 468Register bit
- 469Interrupt Disable register
  - Register bit
- 470Interrupt Enable Status register
  - Register bit
- 471General Status register
- 473Analog-to-Digital Converter (ADC) Module
- T
  - ADC DMA procedure
  - 474. .
    - 475ADC control and status registers
    - ADC Configuration register
    - 477ADC Clock Configuration register
    - ADC Output Registers 0-7
- Timing
479T
- Electrical characteristics
  - 480Recommended operating conditions
  - Power dissipation The table below shows the maximum power dissipation for I/O and core:
    - aVDDA: Ratings of I/O cells for 3.3V interface.
- 481DC electrical characteristics
  - aVSS = 0V (GND)
    - I
- 482Reset and edge sensitive input timing requirements
- 484Memory Timing
  - Notes:
  - 485SDRAM burst read (16-bit)
  - 486SDRAM burst read (16 bit), CAS latency = 3
  - 487SDRAM burst write (16 bit)
  - 488SDRAM burst read (32 bit)
  - 489SDRAM burst read (32 bit), CAS latency = 3
  - 490SDRAM burst write (32-bit)
  - 491SDRAM load mode
  - 492SDRAM refresh mode
  - 501Slow peripheral acknowledge timing
  - The table below describes the values shown in the slow peripheral acknowledge timing diagrams.
  - 502Slow peripheral acknowledge read
  - Slow peripheral acknowledge write
  - for slowest AHB bus clock of 51.6 MHz.
  - 503Ethernet MII timing
  - 507SPI master mode 0 and 1: 2-byte
  - SPI master mode2 and 3: 2-byte
  - 508SPI slave mode 0 and 1: 2-byte
  - SPI slave mode 2 and 3: 2-byte
- 509Reset and hardware strapping timing
- 510JTAG timing
- 511Clock timing
- Change log
517T
- Revision B
- Revision C

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