Remote Operation
Monitoring the Instrument
The STATus:PRESet command clears all event registers and sets all bits in the event enable registers. Use the *CLS common command to clear all event registers and all queues except the output queue. If *CLS is sent immediately following a program message terminator, the output queue is also cleared. In addition, the request for the *OPC bit is also cleared.
For an example program using the status registers, refer to “Example 9. Monitoring the status registers” on page
Status Byte
The Status Byte contains summary bits that monitor activity in the other status registers and queues. The register’s bits are set and cleared by summary bits from other registers or queues. If a bit in the Status Byte goes high, query the value of the source register to determine the cause.
Command | Use |
Returns the status byte value. Reads bit 6 as the | |
| Request Service (RQS) bit and clears the bit |
| which clears the SRQ interrupt. |
*STB? common command | Returns the status byte value. Reads bit 6 as the |
| Master Summary Status (MSS) and does not |
| clear the bit or have any effect on the SRQ inter- |
| rupt. |
*SRE common command | Sets or reads the event enable register value |
| (mask). |
Standard Status Structure
The Standard Status Structure monitors the following instrument status events: operation complete, query error, device dependent error, execution error, and command error. When one of these events occurs, the event sets the corresponding bit in the register.
Command | Use |
*ESR? common command | Returns and clears the value of the event regis- |
| ter. |
*OPC common command | When all operations have finished, sets bit 0 of |
| the event register. The query returns a 1 when |
| all operations have finished. |
*ESE common command | Sets or returns the value of the event enable reg- |
| ister (mask). |