Intel IXC1100, IXP42X 3.6.5 Debug Exceptions

Intel® IXP42X product line and IXC1100 control plane processors—Intel XScale® Processor
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
DM September 2006
92 Order Number: 252480-006US
3.6.4.3 Vector Trap Bits (TF,TI,TD,TA,TS,TU,TR)
The Vector Trap bits allow instruction breakpoints to be set on exception vectors
without using up any of the breakpoint registers. When a bit is set, it acts as if an
instruction breakpoint was set up on the corresponding exception vector. A debug
exception is generated before the instruction in the exception vector executes.
Software running on IXP42X product line and IXC1100 control plane processors must
set the Global Enable bit and the debugger must set the Halt Mode bit and the
appropriate vector trap bit through JTAG to set up a non-reset vector trap.
To set up a reset vector trap, the debugger sets the Halt Mode bit and reset vector trap
bit through JTAG. The Global Enable bit does not effect the reset vector trap. A reset
vector trap can be set up before or during a processor reset. When processor reset is
de-asserted, a debug exception occurs before the instruction in the reset vector
executes.
3.6.4.4 Sticky Abort Bit (SA)
The Sticky Abort bit is only valid in Halt mode. It indicates a data abort occurred within
the Special Debug State (see “Halt Mode” on page 93). Since Special Debug State
disables all exceptions, a data abort exception does not occur. However, the processor
sets the Sticky Abort bit to indicate a data abort was detected. The debugger can use
this bit to determine if a data abort was detected during the Special Debug State. The
sticky abort bit must be cleared by the debug handler before exiting the debug handler.
3.6.4.5 Method of Entry Bits (MOE)
The Method of Entry bits specify the cause of the most recent debug exception. When
multiple exceptions occur in parallel, the processor places the highest priority exception
(based on the priorities in Tabl e 34) in the MOE field.
3.6.4.6 Trace Buffer Mode Bit (M)
The Trace Buffer Mode bit selects one of two trace buffer modes:
• Wrap-around mode — Trace buffer fills up and wraps around until a debug
exception occurs.
• Fill-once mode — The trace buffer automatically generates a debug exception
(trace buffer full break) when it becomes full.
3.6.4.7 Trace Buffer Enable Bit (E)
The Trace Buffer Enable bit enables and disables the trace buffer. Both DCSR.e and
DCSR.ge must be set to enable the trace buffer. The processor automatically clears this
bit to disable the trace buffer when a debug exception occurs. For more details on the
trace buffer refer to “Trace Buffer” on page109.
3.6.5 Debug Exceptions
A debug exception causes the processor to re-direct execution to a debug event
handling routine. IXP42X product line and IXC1100 control plane processors’ debug
architecture defines the following debug exceptions:
• Instruction breakpoint
• Data breakpoint
• Software breakpoint
• External debug break