Receive Controller
and ProcessorThis component recognizes the SP Switch segments and assembles them into IP packets in the 16 MB buffer. Up to 256 IP datagrams can be handled simultaneously. When a complete IP packet has been received, the Receive Controller sends the packet to the FIFO (1) queue for transfer to the serial daughter card.
Buffer (1)This component is segmented into 256 64 KB IP packet buffers. It is used to reassemble IP packets before sending them to the FIFO queue, as switch data segments may arrive out of order and interleaved with segments belonging to different IP packets.
FIFO (1)This component is used to transfer complete IP packets to the serial daughter card and even the flow of data between the SP and GRF crosspoint switch.
FIFO (2)This component receives IP packets from the serial daughter card and transfers them to Buffer (2).
Buffer (2)This buffer is used to temporarily store the IP packet while its IP address is examined and a proper SP Switch route is set up to transfer the packet through the SP Switch.
Send Controller
and ProcessorThis component is notified when an IP packet is received in the FIFO (2) queue and sets up a DMA transfer to send the packet to Buffer (2). The Send Processor looks up the IP address in the packet header and determines the SP Switch route for the packet, before notifying the Send Controller to send the packet to the Send TBIC from Buffer (2).
Send TBICThis component receives data from Buffer (2) and sends it in SP Switch data segments to the SP Switch.
2.3.7 Media Card Performance
The SP Switch Router adapter has the following performance characteristics:
•It is able to transfer up to 100 MB per second. The limiting factor is the crosspoint switch connection bandwidth.
