Renesas SH7781 manuals
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1692 pages 7.74 Mb
Revision Date: Jan. 10 , 2008 32 SH7785Rev.1.00 5 Preface 9 Contents 31 Section 1 Overview 1.1 Features of the SH7785 1. Overview Rev.1.00 Jan. 10, 2008 Page 13 of 1658 REJ09B0261-0100 43 1.2 Block Diagram A block diagram of the SH7785 is given as figure 1.1. Figure 1.1 SH7785 Block Diagram 1. Overview Rev.1.00 Jan. 10, 2008 Page 14 of 1658 REJ09B0261-0100 44 1.3 Pin Arrangement Table Table 1.2 Pin Function 45 1. Overview Rev.1.00 Jan. 10, 2008 Page 15 of 1658 REJ09B0261-0100 46 1. Overview Rev.1.00 Jan. 10, 2008 Page 16 of 1658 REJ09B0261-0100 47 1. Overview Rev.1.00 Jan. 10, 2008 Page 17 of 1658 REJ09B0261-0100 48 1. Overview Rev.1.00 Jan. 10, 2008 Page 18 of 1658 REJ09B0261-0100 49 1. Overview Rev.1.00 Jan. 10, 2008 Page 19 of 1658 REJ09B0261-0100 50 1. Overview Rev.1.00 Jan. 10, 2008 Page 20 of 1658 REJ09B0261-0100 1. Overview Rev.1.00 Jan. 10, 2008 Page 21 of 1658 REJ09B0261-0100 51 Note: * This pin must be pulled-down to GND. 1. Overview Rev.1.00 Jan. 10, 2008 Page 22 of 1658 REJ09B0261-0100 1.4 Pin Arrangement Package: 436-pin FC-BGA, 19 mm x 19 mm, ball pitch: 0.8 mm Figure 1.2 SH7785 Pin Arrangement (Top View) 52 PKG TOP VIEW53 PKG BTM VIEWFigure 1.3 SH7785 Pin Arrangement (Bottom View) Rev.1.00 Jan. 10, 2008 Page 23 of 1658 REJ09B0261-0100 1. Overview Rev.1.00 Jan. 10, 2008 Page 24 of 1658 REJ09B0261-0100 54 1.5 Physical Memory Address Map Figure 1.4 Relationship between AREASEL Bits and Physical Memory Address Map 2. Programming Model Rev.1.00 Jan. 10, 2008 Page 25 of 1658 REJ09B0261-0100 55 Section 2 Programming Model 75 Section 3 Instruction Set 95 Section 4 Pipelining I3 ID E1 E2 E3 WB Figure 4.1 Basic Pipelines 4.1 Pipelines I1 I2 ID FS1 FS2 FS4FS3 FS I1 I2 I3 ID FE1 FE2 FE3 FE4 FE5 FE6 FS 1. General Pipeline 2. General Load/Store Pipeline 3. Special Pipeline 4. Special Load/Store Pipeline 5. Floating-Point Pipeline 6. Floating-Point Extended Pipeline 96 ,4. Pipelining 97 Figure 4.2 Instruction Execution Patterns (1) Rev.1.00 Jan. 10, 2008 Page 67 of 1658 REJ09B0261-0100 4. Pipelining 98 Figure 4.2 Instruction Execution Patterns (2) Rev.1.00 Jan. 10, 2008 Page 68 of 1658 REJ09B0261-0100 4. Pipelining 99 Figure 4.2 Instruction Execution Patterns (3) Rev.1.00 Jan. 10, 2008 Page 69 of 1658 REJ09B0261-0100 (Branch to the next instruction of PREFI.) (Branch to the next instruction of ICBI.) MOV.[BWL], MOV.[BWL] @(d,GBR) (3-5) LDTLB: 1 issue cycle (3-6) ICBI: 8 issue cycles + 5 cycles + 4 branch cycle (3-7) PREFI: 5 issue cycles + 5 cycles + 4 branch cycle (3-8) MOVLI.L: 1 issue cycle (3-9) MOVCO.L: 1 issue cycle (3-10) MOVUA.L: 2 issue cycles 5 cycles (min.) 4. Pipelining 100 Figure 4.2 Instruction Execution Patterns (4) Rev.1.00 Jan. 10, 2008 Page 70 of 1658 REJ09B0261-0100 4. Pipelining 101 Figure 4.2 Instruction Execution Patterns (5) Rev.1.00 Jan. 10, 2008 Page 71 of 1658 REJ09B0261-0100 4. Pipelining 102 Figure 4.2 Instruction Execution Patterns (6) Rev.1.00 Jan. 10, 2008 Page 72 of 1658 REJ09B0261-0100 4. Pipelining 103 Figure 4.2 Instruction Execution Patterns (7) Rev.1.00 Jan. 10, 2008 Page 73 of 1658 REJ09B0261-0100 4. Pipelining 104 Figure 4.2 Instruction Execution Patterns (8) Rev.1.00 Jan. 10, 2008 Page 74 of 1658 REJ09B0261-0100 4. Pipelining 105 Figure 4.2 Instruction Execution Patterns (9) Rev.1.00 Jan. 10, 2008 Page 75 of 1658 REJ09B0261-0100 4. Pipelining Rev.1.00 Jan. 10, 2008 Page 76 of 1658 REJ09B0261-0100 106 4.2 Parallel-Executability 109 4.3 Issue Rates and Execution Cycles 119 Section 5 Exception Handling 155 Section 6 Floating-Point Unit (FPU) 173 Section 7 Memory Management Unit (MMU) 241 Section 8 Caches 273 Section 9 On-Chip Memory 293 Section 10 Interrupt Controller (INTC) 377 Section 11 Local Bus State Controller (LBSC) 11.1 Features 380 11.2 Input/Output Pins Table 11.1 shows the LBSC pin configuration. Table 11.1 Pin Configuration 384 11.3 Overview of Areas 392 11.4 Register Descriptions 417 11.5 Operation 11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 388 of 1658 REJ09B0261-0100 418 Table 11.6 64-Bit External Device/Big Endian Access and Data Alignment (1) 419 Table 11.7 64-Bit External Device/Big Endian Access and Data Alignment (2) 420 Table 11.8 32-Bit External Device/Big-Endian Access and Data Alignment 421 Table 11.9 16-Bit External Device/Big-Endian Access and Data Alignment 422 Table 11.10 8-Bit External Device/Big-Endian Access and Data Alignment 11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 393 of 1658 REJ09B0261-0100 423 Table 11.11 64-Bit External Device/Little Endian Access and Data Alignment (1) 424 Table 11.12 64-Bit External Device/Little Endian Access and Data Alignment (2) 425 Table 11.13 32-Bit External Device/Little-Endian Access and Data Alignment 426 Table 11.14 16-Bit External Device/Little-Endian Access and Data Alignment 427 Table 11.15 8-Bit External Device/Little-Endian Access and Data Alignment 11. Local Bus State Controller (LBSC) 434 Figure 11.5 Basic Timing of SRAM Interface Rev.1.00 Jan. 10, 2008 Page 404 of 1658 REJ09B0261-0100 11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 405 of 1658 REJ09B0261-0100 435 Figure 11.6 Example of 32-Bit Data Width SRAM Connection 11. Local Bus State Controller (LBSC) 436 Figure 11.7 Example of 16-Bit Data Width SRAM Connection Rev.1.00 Jan. 10, 2008 Page 406 of 1658 REJ09B0261-0100 11. Local Bus State Controller (LBSC) 438 Figure 11.9 SRAM Interface Wait Timing (Software Wait Only) Rev.1.00 Jan. 10, 2008 Page 408 of 1658 REJ09B0261-0100 11. Local Bus State Controller (LBSC) 441 Figure 11.11 SRAM Interface Wait Timing (Read-Strobe/Write-Strobe Timing Setting) Rev.1.00 Jan. 10, 2008 Page 411 of 1658 REJ09B0261-0100 443 Figure 11.12 Burst ROM Basic Timing 444 Figure 11.13 Burst ROM Wait Timing 11. Local Bus State Controller (LBSC) 445 Figure 11.14 Burst ROM Wait Timing Rev.1.00 Jan. 10, 2008 Page 415 of 1658 REJ09B0261-0100 11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 418 of 1658 REJ09B0261-0100 448 Table 11.16 Relationship between Address and CE when Using PCMCIA Interface 11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 419 of 1658 REJ09B0261-0100 449 Legend: : Don't care L: Low level H: High level 11. Local Bus State Controller (LBSC) 450 Figure 11.16 Example of PCMCIA Interface Rev.1.00 Jan. 10, 2008 Page 420 of 1658 REJ09B0261-0100 11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 421 of 1658 REJ09B0261-0100 451 Figure 11.17 Basic Timing for PCMCIA Memory Card Interface 11. Local Bus State Controller (LBSC) 452 Figure 11.18 Wait Timing for PCMCIA Memory Card Interface Rev.1.00 Jan. 10, 2008 Page 422 of 1658 REJ09B0261-0100 11. Local Bus State Controller (LBSC) 454 Figure 11.19 Basic Timing for PCMCIA I/O Card Interface Rev.1.00 Jan. 10, 2008 Page 424 of 1658 REJ09B0261-0100 11. Local Bus State Controller (LBSC) 455 Figure 11.20 Wait Timing for PCMCIA I/O Card Interface Rev.1.00 Jan. 10, 2008 Page 425 of 1658 REJ09B0261-0100 11. Local Bus State Controller (LBSC) 456 Figure 11.21 Dynamic Bus Sizing Timing for PCMCIA I/O Card Interface Rev.1.00 Jan. 10, 2008 Page 426 of 1658 REJ09B0261-0100 460 11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 430 of 1658 REJ09B0261-0100 461 11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 431 of 1658 REJ09B0261-0100 462 11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 432 of 1658 REJ09B0261-0100 463 11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 433 of 1658 REJ09B0261-0100 464 11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 434 of 1658 REJ09B0261-0100 465 11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 435 of 1658 REJ09B0261-0100 466 11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 436 of 1658 REJ09B0261-0100 467 11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 437 of 1658 REJ09B0261-0100 468 11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 438 of 1658 REJ09B0261-0100 469 11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 439 of 1658 REJ09B0261-0100 470 11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 440 of 1658 REJ09B0261-0100 11. Local Bus State Controller (LBSC) 472 Figure 11.37 Example of Byte Control SRAM with 64-Bit Data Width Rev.1.00 Jan. 10, 2008 Page 442 of 1658 REJ09B0261-0100 473 Figure 11.38 Basic Read Cycle of Byte Control SRAM (No Wait) 11. Local Bus State Controller (LBSC) 474 Figure 11.39 Wait State Timing of Byte Control SRAM Rev.1.00 Jan. 10, 2008 Page 444 of 1658 REJ09B0261-0100 11. Local Bus State Controller (LBSC) Rev.1.00 Jan. 10, 2008 Page 445 of 1658 REJ09B0261-0100 475 Figure 11.40 Wait State Timing of Byte Control SRAM (One Internal Wait + One External Wait) 477 Figure 11.41 Wait Cycles between Access Cycles (Access Size Is 4 Bytes) 11. Local Bus State Controller (LBSC) 479 Figure 11.42 Arbitration Sequence Rev.1.00 Jan. 10, 2008 Page 449 of 1658 REJ09B0261-0100 483 487 Section 12 DDR2-SDRAM Interface (DBSC2) 12.1 Features 490 12.2 Input/Output Pins Table 12.1 shows the pin configuration of the DBSC2. Table 12.1 Pin Configuration of the DBSC2 Notes: 1. SDRAM pins s hould be connected as shown below. 2. SDRAM pins should be connected as shown below. 493 3. SDRAM pins should be connected as shown below. 4. SDRAM pins should be connected as shown below. 494 5. SDRAM pins should be connected as shown below. 6. SDRAM pins should be connected as shown below. 495 12.3 Data Alignment 509 12.4 Register Descriptions 542 12.5 DBSC2 Operation 552 12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 522 of 1658 REJ09B0261-0100 553 12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 523 of 1658 REJ09B0261-0100 554 12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 524 of 1658 REJ09B0261-0100 555 12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 525 of 1658 REJ09B0261-0100 556 12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 526 of 1658 REJ09B0261-0100 557 12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 527 of 1658 REJ09B0261-0100 558 12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 528 of 1658 REJ09B0261-0100 559 12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 529 of 1658 REJ09B0261-0100 561 12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 531 of 1658 REJ09B0261-0100 562 12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 532 of 1658 REJ09B0261-0100 563 12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 533 of 1658 REJ09B0261-0100 564 12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 534 of 1658 REJ09B0261-0100 12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 537 of 1658 REJ09B0261-0100 567 Figure 12.14 tRP, tRCD, CL, and tRAS 569 12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 539 of 1658 REJ09B0261-0100 570 12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 540 of 1658 REJ09B0261-0100 571 12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 541 of 1658 REJ09B0261-0100 572 12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 542 of 1658 REJ09B0261-0100 573 12. DDR2-SDRAM Interface (DBSC2) Rev.1.00 Jan. 10, 2008 Page 543 of 1658 REJ09B0261-0100 12. DDR2-SDRAM Interface (DBSC2) 575 Figure 12.21 ODT Control Signal when CL = 4 Rev.1.00 Jan. 10, 2008 Page 545 of 1658 REJ09B0261-0100 581 Section 13 PCI Controller (PCIC) 13.1 Features 584 13.2 Input/Output Pins Table 13.1 shows the pin configuration of the PCIC. Table 13.1 Signal Descriptions 13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 557 of 1658 REJ09B0261-0100 587 13.3 Register Descriptions 660 13.4 Operation 13.4.1 Supported PCI Commands Table 13.4 Supported PCI Commands 13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 637 of 1658 REJ09B0261-0100 667 Figure 13.7 Endian Conversion from SuperHyway Bus to PCI Bus (Non-Byte Swapping: TBS = 0) 13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 638 of 1658 REJ09B0261-0100 668 Figure 13.8 Endian Conversion from SuperHyway Bus to PCI Local Bus (Byte Swapping: TBS = 1) 13. PCI Controller (PCIC) 669 Figure 13.9 Data Alignments for SuperHyway Bus and PCI Bus Rev.1.00 Jan. 10, 2008 Page 639 of 1658 REJ09B0261-0100 13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 642 of 1658 REJ09B0261-0100 672 Figure 13.12 I/O Access from PCI Bus to SuperHyway Bus 13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 644 of 1658 REJ09B0261-0100 674 Figure 13.13 Endian Conversion from PCI Bus to SuperHyway Bus (Non-Byte Swapping: TBS = 0) 13. PCI Controller (PCIC) Rev.1.00 Jan. 10, 2008 Page 645 of 1658 REJ09B0261-0100 675 Figure 13.14 Endian Conversion from PCI Bus to SuperHyway Bus (Byte Swapping: TBS = 1) 13. PCI Controller (PCIC) 676 Figure 13.15 Data Alignments for SuperHyway Bus and PCI Bus Rev.1.00 Jan. 10, 2008 Page 646 of 1658 REJ09B0261-0100 13. PCI Controller (PCIC) 684 Figure 13.20 Master Read Cycle in Host Mode (Single) Rev.1.00 Jan. 10, 2008 Page 654 of 1658 REJ09B0261-0100 13. PCI Controller (PCIC) 685 Figure 13.21 Master Write Cycle in Normal Mode (Burst) Rev.1.00 Jan. 10, 2008 Page 655 of 1658 REJ09B0261-0100 13. PCI Controller (PCIC) 686 Figure 13.22 Master Read Cycle in Normal Mode (Burst) Rev.1.00 Jan. 10, 2008 Page 656 of 1658 REJ09B0261-0100 13. PCI Controller (PCIC) 688 Figure 13.23 Target Read Cycle in Normal Mode (Single) Rev.1.00 Jan. 10, 2008 Page 658 of 1658 REJ09B0261-0100 13. PCI Controller (PCIC) 689 Figure 13.24 Target Write Cycle in Normal Mode (Single) Rev.1.00 Jan. 10, 2008 Page 659 of 1658 REJ09B0261-0100 13. PCI Controller (PCIC) 690 Figure 13.25 Target Memory Read Cycle in Host Mode (Burst) Rev.1.00 Jan. 10, 2008 Page 660 of 1658 REJ09B0261-0100 13. PCI Controller (PCIC) 691 Figure 13.26 Target Memory Write Cycle in Host Mode (Burst) Rev.1.00 Jan. 10, 2008 Page 661 of 1658 REJ09B0261-0100 13. PCI Controller (PCIC) 693 Figure 13.28 Target Memory Read Cycle in Host Bus Bridge Mode (Burst, with Stepping) Rev.1.00 Jan. 10, 2008 Page 663 of 1658 REJ09B0261-0100 695 Section 14 Direct Memory Access Controller (DMAC) 763 Section 15 Clock Pulse Generator (CPG) 789 Section 16 Watchdog Timer and Reset (WDT) 811 Section 17 Power-Down Mode 829 Section 18 Timer Unit (TMU) 847 Section 19 Display Unit (DU) 999 Section 20 Graphics Data Translation Accelerator (GDTA) 1063 Section 21 Serial Communication Interface with FIFO (SCIF) 21.1 Features 1069 21.2 Input/Output Pins 21. Serial Communication Interface with FIFO (SCIF) Rev.1.00 Jan. 10, 2008 Page 1040 of 1658 REJ09B0261-0100 1070 21.3 Register Descriptions 1101 21.4 Operation 1102 Table 21.4 SCSMR Settings for Serial Transfer Format Selection 1103 Table 21.5 SCSMR and SCSCR Settings for SCIF Clock Source Selection SCSMR Settings Serial Transfer Format and Frame Length Legend: S: Start bit STOP: Stop bit P: Parity bit 21. Serial Communication Interface with FIFO (SCIF) Rev.1.00 Jan. 10, 2008 Page 1077 of 1658 REJ09B0261-0100 1107 Figure 21.8 shows a sample SCIF initialization flowchart. Figure 21.8 Sample SCIF Initialization Flowchart 21. Serial Communication Interface with FIFO (SCIF) Rev.1.00 Jan. 10, 2008 Page 1078 of 1658 REJ09B0261-0100 1108 Figure 21.9 Sample Serial Transmission Flowchart 21. Serial Communication Interface with FIFO (SCIF) Rev.1.00 Jan. 10, 2008 Page 1080 of 1658 REJ09B0261-0100 1110 Figure 21.10 shows an example of the operation for transmission in asynchronous mode. Figure 21.11 shows an example of the operation when modem control is used. Figure 21.11 Example of Operation Using Modem Control (SCIF_CTS) (Only in Channel 0) 21. Serial Communication Interface with FIFO (SCIF) Rev.1.00 Jan. 10, 2008 Page 1081 of 1658 REJ09B0261-0100 1111 Figure 21.12 Sample Serial Reception Flowchart (1) 21. Serial Communication Interface with FIFO (SCIF) 1112 Figure 21.12 Sample Serial Reception Flowchart (2) Rev.1.00 Jan. 10, 2008 Page 1082 of 1658 REJ09B0261-0100 21. Serial Communication Interface with FIFO (SCIF) 1117 Figure 21.16 Sample SCIF Initialization Flowchart Rev.1.00 Jan. 10, 2008 Page 1087 of 1658 REJ09B0261-0100 21. Serial Communication Interface with FIFO (SCIF) Rev.1.00 Jan. 10, 2008 Page 1088 of 1658 REJ09B0261-0100 1118 Figure 21.17 Sample Serial Transmission Flowchart 21. Serial Communication Interface with FIFO (SCIF) Rev.1.00 Jan. 10, 2008 Page 1090 of 1658 REJ09B0261-0100 1120 Figure 21.19 Sample Serial Reception Flowchart (1) 21. Serial Communication Interface with FIFO (SCIF) 1122 Figure 21.20 Example of SCIF Reception Operation Rev.1.00 Jan. 10, 2008 Page 1092 of 1658 REJ09B0261-0100 21. Serial Communication Interface with FIFO (SCIF) Rev.1.00 Jan. 10, 2008 Page 1093 of 1658 REJ09B0261-0100 1123 Figure 21.21 Sample Flowchart for Transmitting/Receiving Serial Data 1124 21.5 SCIF Interrupt Sources and the DMAC 1126 21.6 Usage Notes 1129 Section 22 Serial I/O with FIFO (SIOF) 1181 Section 23 Serial Peripheral Interface (HSPI) 1201 Section 24 Multimedia Card Interface (MMCIF) 24.1 Features Figure 24.1 shows a block diagram of the MMCIF. Figure 24.1 Block Diagram of MMCIF 1202 24.2 Input/Output Pins Table 24.1 summarizes the pins of the MMCIF. Table 24.1 Pin Configuration 1203 24.3 Register Descriptions 1239 24.4 Operation 1244 24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1214 of 1658 REJ09B0261-0100 24. Multimedia Card Interface (MMCIF) 1245 Figure 24.7 Example of Operational Flow for Commands without Data Transfer Rev.1.00 Jan. 10, 2008 Page 1215 of 1658 REJ09B0261-0100 24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1218 of 1658 REJ09B0261-0100 1248 Figure 24.9 Example of Command Sequence for Commands with Read Data (Block Size > FIFO Size) 24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1219 of 1658 REJ09B0261-0100 1249 Figure 24.10 Example of Command Sequence for Commands with Read Data (Multiple Block Transfer) 24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1220 of 1658 REJ09B0261-0100 1250 Figure 24.11 Example of Command Sequence for Commands with Read Data (Stream Transfer) 24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1221 of 1658 REJ09B0261-0100 1251 Figure 24.12 Example of Operational Flow for Commands with Read Data (Single Block Transfer) 1253 24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1223 of 1658 REJ09B0261-0100 1254 24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1224 of 1658 REJ09B0261-0100 1255 24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1225 of 1658 REJ09B0261-0100 24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1226 of 1658 REJ09B0261-0100 1256 Figure 24.14 Example of Operational Flow for Commands with Read Data (Stream Transfer) 24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1229 of 1658 REJ09B0261-0100 1259 Figure 24.15 Example of Command Sequence for Commands with Write Data (Block Size FIFO Size) 24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1230 of 1658 REJ09B0261-0100 1260 Figure 24.16 Example of Command Sequence for Commands with Write Data (Block Size > FIFO Size) 24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1231 of 1658 REJ09B0261-0100 1261 Figure 24.17 Example of Command Sequence for Commands with Write Data (Multiple Block Transfer) 24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1232 of 1658 REJ09B0261-0100 1262 Figure 24.18 Example of Command Sequence for Commands with Write Data (Stream Transfer) 24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1233 of 1658 REJ09B0261-0100 1263 Figure 24.19 Example of Operational Flow for Commands with Write Data (Single Block Transfer) 1265 24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1235 of 1658 REJ09B0261-0100 1266 24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1236 of 1658 REJ09B0261-0100 1267 24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1237 of 1658 REJ09B0261-0100 24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1238 of 1658 REJ09B0261-0100 1268 Figure 24.21 Example of Operational Flow for Commands with Write Data (Stream Transfer) 1269 24.5 MMCIF Interrupt Sources 1270 24.6 Operations when Using DMA 24. Multimedia Card Interface (MMCIF) 1272 Figure 24.22 Example of Read Sequence Flow (Single Block Transfer) Rev.1.00 Jan. 10, 2008 Page 1242 of 1658 REJ09B0261-0100 24. Multimedia Card Interface (MMCIF) 1273 Figure 24.23 (1) Example of Read Sequence Flow (Open-ended Multiple Block Transfer) Rev.1.00 Jan. 10, 2008 Page 1243 of 1658 REJ09B0261-0100 24. Multimedia Card Interface (MMCIF) 1274 Figure 24.23 (2) Example of Read Sequence Flow (Open-ended Multiple Block Transfer) Rev.1.00 Jan. 10, 2008 Page 1244 of 1658 REJ09B0261-0100 24. Multimedia Card Interface (MMCIF) 1275 Figure 24.23 (3) Example of Read Sequence Flow (Pre-defined Multiple Block Transfer) Rev.1.00 Jan. 10, 2008 Page 1245 of 1658 REJ09B0261-0100 24. Multimedia Card Interface (MMCIF) 1276 Figure 24.23 (4) Example of Read Sequence Flow (Pre-defined Multiple Block Transfer) Rev.1.00 Jan. 10, 2008 Page 1246 of 1658 REJ09B0261-0100 Legend: n (DTI): Number of data transfer end interrupts (DTI) from the start of read sequence 1 2 24. Multimedia Card Interface (MMCIF) 1277 Figure 24.24 Example of Operational Flow for Stream Read Transfer 1279 24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1249 of 1658 REJ09B0261-0100 24. Multimedia Card Interface (MMCIF) 1282 Figure 24.26 (1) Example of Write Sequence Flow (Single Block Transfer) Rev.1.00 Jan. 10, 2008 Page 1252 of 1658 REJ09B0261-0100 24. Multimedia Card Interface (MMCIF) 1283 Figure 24.26 (2) Example of Write Sequence Flow (Single Block Transfer) Rev.1.00 Jan. 10, 2008 Page 1253 of 1658 REJ09B0261-0100 24. Multimedia Card Interface (MMCIF) 1284 Figure 24.27 (1) Example of Write Sequence Flow (Open-ended Multiple Block Transfer) Rev.1.00 Jan. 10, 2008 Page 1254 of 1658 REJ09B0261-0100 24. Multimedia Card Interface (MMCIF) 1285 Figure 24.27 (2) Example of Write Sequence Flow (Open-ended Multiple Block Transfer) Rev.1.00 Jan. 10, 2008 Page 1255 of 1658 REJ09B0261-0100 24. Multimedia Card Interface (MMCIF) 1286 Figure 24.27 (3) Example of Write Sequence Flow (Pre-defined Multiple Block Transfer) Rev.1.00 Jan. 10, 2008 Page 1256 of 1658 REJ09B0261-0100 24. Multimedia Card Interface (MMCIF) 1287 Figure 24.27 (4) Example of Write Sequence Flow (Pre-defined Multiple Block Transfer) Rev.1.00 Jan. 10, 2008 Page 1257 of 1658 REJ09B0261-0100 1 2 Legend: n (DRPI): Number of data response interrupts (DRPI) from the start of write sequence 24. Multimedia Card Interface (MMCIF) 1288 Figure 24.28 Example of Operational Flow for Stream Write Transfer 1290 24. Multimedia Card Interface (MMCIF) Rev.1.00 Jan. 10, 2008 Page 1260 of 1658 REJ09B0261-0100 1291 24.7 Register Accesses with Little Endian Specification 1293 Section 25 Audio Codec Interface (HAC) 1327 Section 26 Serial Sound Interface (SSI) Module 1367 Section 27 NAND Flash Memory Controller (FLCTL) 1407 Section 28 General Purpose I/O Ports (GPIO) 1483 Section 29 User Break Controller (UBC) 1517 Section 30 User Debugging Interface (H-UDI) 1539 Section 31 Register List 31.1 Register Address List 31. Register List Rev.1.00 Jan. 10, 2008 Page 1510 of 1658 REJ09B0261-0100 1540 Table 31.1 Register Address List 1541 31. Register List Rev.1.00 Jan. 10, 2008 Page 1511 of 1658 REJ09B0261-0100 1542 31. Register List Rev.1.00 Jan. 10, 2008 Page 1512 of 1658 REJ09B0261-0100 1543 31. Register List Rev.1.00 Jan. 10, 2008 Page 1513 of 1658 REJ09B0261-0100 1544 31. Register List Rev.1.00 Jan. 10, 2008 Page 1514 of 1658 REJ09B0261-0100 1545 31. Register List Rev.1.00 Jan. 10, 2008 Page 1515 of 1658 REJ09B0261-0100 1546 31. Register List Rev.1.00 Jan. 10, 2008 Page 1516 of 1658 REJ09B0261-0100 1547 31. Register List Rev.1.00 Jan. 10, 2008 Page 1517 of 1658 REJ09B0261-0100 1548 31. Register List Rev.1.00 Jan. 10, 2008 Page 1518 of 1658 REJ09B0261-0100 1549 31. Register List Rev.1.00 Jan. 10, 2008 Page 1519 of 1658 REJ09B0261-0100 1550 31. Register List Rev.1.00 Jan. 10, 2008 Page 1520 of 1658 REJ09B0261-0100 1551 31. Register List Rev.1.00 Jan. 10, 2008 Page 1521 of 1658 REJ09B0261-0100 1552 31. Register List Rev.1.00 Jan. 10, 2008 Page 1522 of 1658 REJ09B0261-0100 1553 31. Register List Rev.1.00 Jan. 10, 2008 Page 1523 of 1658 REJ09B0261-0100 1554 31. Register List Rev.1.00 Jan. 10, 2008 Page 1524 of 1658 REJ09B0261-0100 1555 31. Register List Rev.1.00 Jan. 10, 2008 Page 1525 of 1658 REJ09B0261-0100 1556 31. Register List Rev.1.00 Jan. 10, 2008 Page 1526 of 1658 REJ09B0261-0100 1557 31. Register List Rev.1.00 Jan. 10, 2008 Page 1527 of 1658 REJ09B0261-0100 1558 31. Register List Rev.1.00 Jan. 10, 2008 Page 1528 of 1658 REJ09B0261-0100 1559 31. Register List Rev.1.00 Jan. 10, 2008 Page 1529 of 1658 REJ09B0261-0100 1560 31. Register List Rev.1.00 Jan. 10, 2008 Page 1530 of 1658 REJ09B0261-0100 1561 31. Register List Rev.1.00 Jan. 10, 2008 Page 1531 of 1658 REJ09B0261-0100 31. Register List Rev.1.00 Jan. 10, 2008 Page 1533 of 1658 REJ09B0261-0100 1563 31.2 States of the Registers in the Individual Operating Modes 1564 31. Register List Rev.1.00 Jan. 10, 2008 Page 1534 of 1658 REJ09B0261-0100 1565 31. Register List Rev.1.00 Jan. 10, 2008 Page 1535 of 1658 REJ09B0261-0100 1566 31. Register List Rev.1.00 Jan. 10, 2008 Page 1536 of 1658 REJ09B0261-0100 1567 31. Register List Rev.1.00 Jan. 10, 2008 Page 1537 of 1658 REJ09B0261-0100 31. Register List Rev.1.00 Jan. 10, 2008 Page 1538 of 1658 REJ09B0261-0100 1568 31. Register List Rev.1.00 Jan. 10, 2008 Page 1539 of 1658 REJ09B0261-0100 1569 Table 31.3 States of the Registers in the Individual Operating Modes (2) 1570 31. Register List Rev.1.00 Jan. 10, 2008 Page 1540 of 1658 REJ09B0261-0100 1571 31. Register List Rev.1.00 Jan. 10, 2008 Page 1541 of 1658 REJ09B0261-0100 31. Register List Rev.1.00 Jan. 10, 2008 Page 1542 of 1658 REJ09B0261-0100 1572 Table 31.4 States of the Registers in the Individual Operating Modes (3) 31. Register List Rev.1.00 Jan. 10, 2008 Page 1543 of 1658 REJ09B0261-0100 1573 Table 31.5 States of the Registers in the Individual Operating Modes (4) 1574 31. Register List Rev.1.00 Jan. 10, 2008 Page 1544 of 1658 REJ09B0261-0100 1575 31. Register List Rev.1.00 Jan. 10, 2008 Page 1545 of 1658 REJ09B0261-0100 1576 31. Register List Rev.1.00 Jan. 10, 2008 Page 1546 of 1658 REJ09B0261-0100 1577 31. Register List Rev.1.00 Jan. 10, 2008 Page 1547 of 1658 REJ09B0261-0100 1578 31. Register List Rev.1.00 Jan. 10, 2008 Page 1548 of 1658 REJ09B0261-0100 1579 31. Register List Rev.1.00 Jan. 10, 2008 Page 1549 of 1658 REJ09B0261-0100 1580 31. Register List Rev.1.00 Jan. 10, 2008 Page 1550 of 1658 REJ09B0261-0100 1581 31. Register List Rev.1.00 Jan. 10, 2008 Page 1551 of 1658 REJ09B0261-0100 1582 31. Register List Rev.1.00 Jan. 10, 2008 Page 1552 of 1658 REJ09B0261-0100 31. Register List Rev.1.00 Jan. 10, 2008 Page 1553 of 1658 REJ09B0261-0100 1583 Notes: 1. Bits 2 and 0 ar e undefined. 2. Bits 6, 4, 2 and 0 are undefined. 31. Register List Rev.1.00 Jan. 10, 2008 Page 1554 of 1658 REJ09B0261-0100 1584 Table 31.6 States of the Registers in the Individual Operating Modes (5) 31. Register List Rev.1.00 Jan. 10, 2008 Page 1555 of 1658 REJ09B0261-0100 1585 Table 31.7 States of the Registers in the Individual Operating Modes (6) 1590 Table 31.8 States of the Registers in the Individual Operating Modes (7) Table 31.9 States of the Registers in the Individual Operating Modes (8) 1591 Section 32 Electrical Characteristics 32.1 Absolute Maximum Ratings Table 32.1 Absolute Maximum Ratings*1, 2 1592 32.2 DC Characteristics 1597 32.3 AC Characteristics 1598 32.3.1 Clock and Control Signal Timing Table 32.6 Clock and Control Signal Timing 1599 Figure 32.1 EXTAL Clock Input Timing 32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1570 of 1658 REJ09B0261-0100 1600 Figure 32.2 CLKOUT Clock Output Timing (1) Figure 32.3 CLKOUT Clock Output Timing (2) 32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1571 of 1658 REJ09B0261-0100 1601 Figure 32.4 Power-On Oscillation Settling Time Figure 32.5 PLL Synchronization Settling Time 32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1573 of 1658 REJ09B0261-0100 1603 Figure 32.7 Control Signal Timing Figure 32.8 STATUS Pin Output Timing at Power-On Reset 32. Electrical Characteristics 1605 Figure 32.9 SRAM Bus Cycle: Basic Bus Cycle (No Wait) Rev.1.00 Jan. 10, 2008 Page 1575 of 1658 REJ09B0261-0100 32. Electrical Characteristics 1606 Figure 32.10 SRAM Bus Cycle: Basic Bus Cycle (One Internal Wait Cycle) 1608 32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1578 of 1658 REJ09B0261-0100 32. Electrical Characteristics 1609 Figure 32.13 Burst ROM Bus Cycle (No Wait) Rev.1.00 Jan. 10, 2008 Page 1579 of 1658 REJ09B0261-0100 Legend:CLKOUT A25 to A5 A4 to A0 RD RD/WR T1 T2 TB2 TB1 TB2 TB1 TB2 TB1 DACKn DACKn (DA) 1610 32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1580 of 1658 REJ09B0261-0100 1611 32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1581 of 1658 REJ09B0261-0100 32. Electrical Characteristics 1612 Figure 32.16 Burst ROM Bus Cycle (One Internal Wait Cycle + One External Wait Cycle) Rev.1.00 Jan. 10, 2008 Page 1582 of 1658 REJ09B0261-0100 32. Electrical Characteristics 1613 Figure 32.17 PCMCIA Memory Bus Cycle Rev.1.00 Jan. 10, 2008 Page 1583 of 1658 REJ09B0261-0100 32. Electrical Characteristics 1614 Figure 32.18 PCMCIA I/O Bus Cycle Rev.1.00 Jan. 10, 2008 Page 1584 of 1658 REJ09B0261-0100 32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1585 of 1658 REJ09B0261-0100 1615 Figure 32.19 PCMCIA I/O Bus Cycle (TED = 1, TEH = 1, One Internal Wait Cycle, with Bus Sizing) 32. Electrical Characteristics 1616 Figure 32.20 MPX Basic Bus Cycle (Read) Rev.1.00 Jan. 10, 2008 Page 1586 of 1658 REJ09B0261-0100 32. Electrical Characteristics 1617 Figure 32.21 MPX Basic Bus Cycle (Write) Rev.1.00 Jan. 10, 2008 Page 1587 of 1658 REJ09B0261-0100 32. Electrical Characteristics 1618 Figure 32.22 MPX Bus Cycle (Burst Read) Rev.1.00 Jan. 10, 2008 Page 1588 of 1658 REJ09B0261-0100 32. Electrical Characteristics 1619 Figure 32.23 MPX Bus Cycle (Burst Write) Rev.1.00 Jan. 10, 2008 Page 1589 of 1658 REJ09B0261-0100 32. Electrical Characteristics 1620 Figure 32.24 Memory Byte Control SRAM Bus Cycle 1623 Figure 32.26 MCK Output Clock 32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1594 of 1658 REJ09B0261-0100 1624 Figure 32.27 Command Signal and MCK Output Clock Figure 32.28 MDQS Input Timing at Data Read 32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1595 of 1658 REJ09B0261-0100 MDQS[3:0] (solid line) MDQS[3:0] (dotted line) HiZ HiZ 1625 Figure 32.29 Restriction of MDQS Input Waveform (Read) Figure 32.30 MDQS Output Waveform to MCK (Write) Figure 32.31 MDQS Output Waveform (Write) MDQS[3:0] (solid line) MDQS[3:0] (dotted line) HiZ HiZ 32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1596 of 1658 REJ09B0261-0100 1626 Figure 32.32 MDQS and MDQ/MDM Output Waveform (Write) Figure 32.33 MDQ High-Impedance Time from MDQS (Write) 1627 Figure 32.34 Interrupt Signal Input Timing (1) 32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1598 of 1658 REJ09B0261-0100 1628 Figure 32.35 Interrupt Signal Input Timing (2) Figure 32.36 IRQOUT Timing 32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1600 of 1658 REJ09B0261-0100 1630 Figure 32.37 PCI Clock Input Timing Figure 32.38 PCI Output Signal Timing 1631 Figure 32.40 DREQ/DRAK Signal Timing 1632 Figure 32.41 TCLK Input Timing 1633 Figure 32.42 SCIFn_CLK Input Clock Timing 1634 Figure 32.43 Clock Timing in SCIF I/O Synchronous Mode 1635 Figure 32.44 TCK Input Timing 32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1606 of 1658 REJ09B0261-0100 1636 Figure 32.45 RESET Hold Timing Figure 32.46 H-UDI Data Transfer Timing Figure 32.47 Pin Break Timing 1637 32.3.11 GPIO Signal Timing Table 32.16 GPIO Signal Timing Figure 32.48 GPIO Signal Timing 1638 32.3.12 HSPI Module Signal Timing Table 32.17 HSPI Module Signal Timing Figure 32.49 HSPI Data Output/Input Timing 1639 32.3.13 SIOF Module Signal Timing Table 32.18 SIOF Module Signal Timing Figure 32.50 SIOF_MCLK Input Timing 32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1610 of 1658 REJ09B0261-0100 1640 Figure 32.51 SIOF Transmission/Reception Timing (Master Mode 1, Sampling on Falling Edges) Figure 32.52 SIOF Transmission/Reception Timing (Master Mode 1, Sampling on Rising Edges) 32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1611 of 1658 REJ09B0261-0100 1641 Figure 32.53 SIOF Transmission/Reception Timing (Master Mode 2, Sampling on Falling Edges) Figure 32.54 SIOF Transmission/Reception Timing (Master Mode 2, Sampling on Rising Edges) 32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1612 of 1658 REJ09B0261-0100 1642 Figure 32.55 SIOF Transmission/Reception Timing (Slave Mode 1, Slave Mode 2) 1643 32.3.14 MMCIF Module Signal Timing Table 32.19 MMCIF Module Signal Timing Figure 32.56 MMCIF Transmission Timing 1644 Figure 32.58 HAC Cold Reset Timing 32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1615 of 1658 REJ09B0261-0100 1645 Figure 32.59 HAC Warm Reset Timing Figure 32.60 HAC Clock Input Timing Figure 32.61 HAC Interface Module Signal Timing 1646 32.3.16 SSI Interface Module Signal Timing Table 32.21 SSI Interface Module Signal Timing Figure 32.62 SSI Clock Input/Output Timing Figure 32.63 SSI Transmission Timing (1) 32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1617 of 1658 REJ09B0261-0100 1647 Figure 32.64 SSI Transmission Timing (2) Figure 32.66 SSI Reception Timing (2) t SSIn_SCK SSIn_WS SSIn_SDATA Figure 32.65 SSI Reception Timing (1) 1648 32.3.17 FLCTL Module Signal Timing Table 32.22 NAND-Type Flash Memory Interface Timing 32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1619 of 1658 REJ09B0261-0100 1649 Figure 32.67 Command Issue Timing of NAND-Type Flash Memory Figure 32.68 Address Issue Timing of NAND-Type Flash Memory 32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1620 of 1658 REJ09B0261-0100 1650 Figure 32.69 Data Read Timing of NAND-Type Flash Memory Figure 32.70 Data Write Timing of NAND-Type Flash Memory 32. Electrical Characteristics 1651 Figure 32.71 Status Read Timing of NAND-Type Flash Memory Rev.1.00 Jan. 10, 2008 Page 1621 of 1658 REJ09B0261-0100 1652 Table 32.24 Display Timing Conditions: VDDQ = 3.3 V 0.3 V, Ta = 40C to +85C, GND = VSSQ = 0 V 1653 Table 32.25 Classification of Pins Figure 32.72 PCICLK/DCLKIN Clock Input Timing 32. Electrical Characteristics Rev.1.00 Jan. 10, 2008 Page 1624 of 1658 REJ09B0261-0100 1654 Figure 32.73 Display Timing (with Respect to PCICLK/DCLKIN) Figure 32.74 Display Timing (with Respect to DEVSEL/DCLKOUT) 1655 32.4 AC Characteristic Test Conditions 1658 B. Mode Pin Settings 1661 C. Pin Functions 1683 D. Turning On and Off Power Supply 1686 E. Version Registers (PVR, PRR) Processor Version Register (PVR) Product Register (PRR) 1687 F. Product Lineup 1692 SH7785 Hardware Manual
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