29. User Break Controller (UBC)
Rev.1.00 Jan. 10, 2008 Page 1464 of 1658
REJ09B0261-0100
• CRR1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0000000000000000
PCB BIE
RRRRRRRRRRRRRRRR
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0010000000000000
RRRRRRRRRRRRRRR/WR/W
Bit :
Initial value :
R/W:
Bit :
Initial value :
R/W:
Bit Bit Name
Initial
Value R/W Description
31 to 14 — All 0 R Reserved
For read/write in this bit, refer to General Precautions
on Handling of Product.
13 — 1 R Reserved
This bit is always read as 1. The write value should
always be 1.
12 to 2 — All 0 R Reserved
For read/write in this bit, refer to General Precautions
on Handling of Product.
1 PCB 0 R/W PC Break Select
Specifies either before or after instruction execution as
the break timing for the instruction fetch cycle. This bit
is invalid for breaks other than ones for the instruction
fetch cycle.
0: Sets the PC break before instruction execution.
1: Sets the PC break after instruction execution.
0 BIE 0 R/W Break Enable
Specifies whether or not to request a break when the
match condition is satisfied for the channel.
0: Does not request a break.
1: Requests a break.