19. Display Unit (DU)
Rev.1.00 Jan. 10, 2008 Page 895 of 1658
REJ09B0261-0100
19.3.31 Plane n Mode Register (PnMR) (n = 1 to 6) The plane n mode registers (PnMR, n = 1 to 6) set the display operation for plane n.
R/W:
Internal update:
R/W:
Internal update:
161718192021222324252627282931 30Bit:
Initial value:
R/WR/WRRR/WRRRRRRRRRRR
OO O
0000000000000000
PnWAEPnTC
PnYCDF— —
R/WR/WRRR/WR/WRR/WR/WR/WRRR/WR/WR R/W
OO OO OOO OO O
0000000000000000
PnDDF
PnBM
PnDCPnCPSL
PnSPIM
01234567891011121315 14Bit:
Initial value:
Bit Bit Name
Initial
Value R/W
Internal
Update Description
31 to 21 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
20 PnYCDF 0 R/W Yes Plane n YC Data Format
0: Sets the order of YC data to UYVY format.
1: Sets the order of YC data to YUYV format.
19, 18 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
17 PnTC 0 R/W Yes Plane n Transparent Color
0: When set to 8 bits/pixel display, the
transparent color is the color set in the plane
n transparent color 1 register (PnTC1R)
1: When set to 8 bits/pixel display, any of the
transparent colors set in CP1TR to CP4TR
can be a transparent color
CP1TR to CP4TR to be used are determined
by the setting of the PnCPSL bit.
16 PnWAE 0 R/W Yes Plane n Wrap Around Enable
0: Wraparound is not performed for plane n
1: Wraparound is performed for plane n
15 0 R Reserved
This bit is always read as 0. The write value
should always be 0.