Renesas SH7781 32.3.12 HSPI Module Signal Timing Table 32.17 HSPI Module Signal Timing , Figure 32.49 HSPI Data Output/Input Timing

32. Electrical Characteristics
Rev.1.00 Jan. 10, 2008 Page 1608 of 1658
REJ09B0261-0100
32.3.12 HSPI Module Signal Timing
Table 32.17 HSPI Module Signal Timing
Item Symbol Min. Max. Unit Figure
HSPI clock frequency (master) TSPICYC — Pck/8 MHz 32.49
HSPI clock frequency (slave) Pck/12
HSPI clock high level width tSPIHW 60 — ns
HSPI clock low level width tSPILW 60 — ns
HSPI_TX setup time tSUSPITX — 20 ns
HSPI_TX delay time tDSPITX — 20 ns
HSPI_RX setup time tSUSPIRX 20 — ns
HSPI_RX hold time tHLSPIRX 20 — ns
HSPI_CS lead time tcCSLEAD 100 — ns
Note: Pck is the frequency of the peripheral clock.
HSPI_CS
t
SPICYC
t
CSLEAD
t
SUSPITX
t
SUSPIRX
t
SUSPIRX
t
HLSPIRX
t
SUSPITX
t
DSPITX
t
HLSPIRX
t
DSPITX
t
SPILW
t
SPIHW
(CLKP = 0)
HSPI_CLK
(CLKP = 1)
HSPI_CLK
(LMSB = 0)
HSPI_TX
(LMSB = 1)
HSPI_TX
HSPI_RX
HSPI_RX
MSB-1MSB
MSB
MSB
MSB MSB-1
MSB-1
MSB-1 MSB-2
Figure 32.49 HSPI Data Output/Input Timing