13. PCI Controller (PCIC)
Rev.1.00 Jan. 10, 2008 Page 617 of 1658
REJ09B0261-0100
(17) PCI Memory Bank Mask Register 0 (PCIMBMR0) This register is the mask register for PCIMBR0. This register specifies the memory space size on the PCI bus for a memory read or write to the PCI memory space 0 by the CPU or DMAC. See section 13.4.3 (2), Accessing PCI Memory Space.
SH R/W:
PCI R/W:
SH R/W:
PCI R/W:
161718192021222324252627282931 30Bit:
Initial value:
RRR/WR/W
RRRR
R/WR/WR/WR/W
0000000000000000
——
——
RRRRRRRRRRRR
RRRRRRR R
0000000000000000
MSBAM0— —
01234567891011121315 14Bit:
Initial value:
Bit Bit Name
Initial
Value R/W Description
31 to 24 All 0 SH: R
PCI:
Reserved
These bits are always read as 0. The write value
should always be 0.
23 to 18 MSBAM0 000000 SH: R/W
PCI:
PCI Memory Space 0 Bank Address Mask (6 bits)
0000 00: 256 kbytes
0000 01: 512 kbytes
0000 11: 1 Mbyte
0001 11: 2 Mbytes
0011 11: 4 Mbytes
0111 11: 8 Mbytes
1111 11: 16 Mbytes
Other than above: Setting prohibited
17 to 0 All 0 SH: R
PCI:
Reserved
These bits are always read as 0. The write value
should always be 0.