19. Display Unit (DU)
Rev.1.00 Jan. 10, 2008 Page 854 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value R/W
Internal
Update Description
9 RICL Undefined W None Vertical Blanking Flag Clear
0: The RINT flag in DSSR is not changed.
1: The RINT flag in DSSR is cleared to 0.
8 HBCL Undefined W None Vertical Blanking Flag Clear
0: The HBK flag in DSSR is not changed.
1: The HBK flag in DSSR is cleared to 0.
7 to 0 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
19.3.5 Display Unit Interrupt Enable Register (DIER) The display unit interrupt enable register (DIER) is a register which enables interrupts to the CPU the causes of which are internal states of the display unit (DU) reflected in DSSR. When bits are set in this register, if bits in the same bit positions in DSSR are set, an interrupt is issued to the CPU.
R/W:
Internal update:
R/W:
Internal update:
161718192021222324252627282931 30Bit:
Initial value:
RRRRRRRRRRRRRRRR
0000000000000000
RRRRRRRRR/WR/WRR/WRRR/W R/W
0000000000000000
HBERIE
VBE
TVE FRE
01234567891011121315 14Bit:
Initial value: