Main
Revision Date: Jan. 10 ,
2008
32
SH7785
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Notes regarding these materials
General Precautions in the Handling of MPU/MCU Products
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Preface
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Contents
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Section 1 Overview
1.1 Features of the SH7785
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1. Overview
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1.2 Block Diagram
A block diagram of the SH7785 is given as figure 1.1.
Figure 1.1 SH7785 Block Diagram
1. Overview
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1.3 Pin Arrangement Table
Table 1.2 Pin Function
1. Overview
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1. Overview
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1. Overview
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1. Overview
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1. Overview
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Note: * This pin must be pulled-down to GND.
1. Overview
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1.4 Pin Arrangement
PKG TOP VIEW
1. Overview
PKG BTM VIEW
Figure 1.3 SH7785 Pin Arrangement (Bottom View)
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1. Overview
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1.5 Physical Memory Address Map
Figure 1.4 Relationship between AREASEL Bits and Physical Memory Address Map
2. Programming Model
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Section 2 Programming Model
Figure 2.1 Data Formats
2.1 Data Formats
The data formats supported in this LSI are shown in figure 2.1.
2.2 Register Descriptions
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Table 2.1 Initial Register Values
2. Programming Model
Figure 2.2 CPU Register Configuration in Each Processing Mode
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(a) Register configuration in user mode
(b) Register configuration in privileged mode (RB = 1)
(c) Register configuration in privileged mode (RB = 0)
Figure 2.3 General Registers
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2. Programming Model
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Figure 2.4 Floating-Point Registers
2.2.4 Control Registers (1) Status Register (SR)
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(4) Floating-Point Status/Control Register (FPSCR)
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2.3 Memory-Mapped Registers
2.4 Data Formats in Registers
2.5 Data Formats in Memory
2.6 Processing States
Figure 2.8 Processing State Transitions
2.7 Usage Notes
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Section 3 Instruction Set
3.1 Execution Environment
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3.2 Addressing Modes
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2
+
4
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disp (sign-extended)
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3.3 Instruction Set
Table 3.4 Fixed-Point Transfer Instructions
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Table 3.5 Arithmetic Operation Instructions
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Table 3.6 Logic Operation Instructions
Table 3.7 Shift Instructions
Table 3.8 Branch Instructions
Table 3.9 System Control Instructions
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Table 3.10 Floating-Point Single-Precision Instructions
Table 3.11 Floating-Point Double-Precision Instructions
Table 3.12 Floating-Point Control Instructions
Table 3.13 Floating-Point Graphics Acceleration Instructions
Note: * sqrt(FRn) is the square root of FRn.
4. Pipelining
Section 4 Pipelining
I3 ID E1 E2 E3 WB
Figure 4.1 Basic Pipelines
I1 I2
4.1 Pipelines
,
4. Pipelining
Figure 4.2 Instruction Execution Patterns (1)
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4. Pipelining
Figure 4.2 Instruction Execution Patterns (2)
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4. Pipelining
Figure 4.2 Instruction Execution Patterns (3)
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(Branch to the next instruction of PREFI.)
(Branch to the next instruction of ICBI.)
MOV.[BWL], MOV.[BWL] @(d,GBR)
Figure 4.2 Instruction Execution Patterns (4)
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4. Pipelining
Figure 4.2 Instruction Execution Patterns (5)
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4. Pipelining
Figure 4.2 Instruction Execution Patterns (6)
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4. Pipelining
Figure 4.2 Instruction Execution Patterns (7)
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4. Pipelining
Figure 4.2 Instruction Execution Patterns (8)
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4. Pipelining
Figure 4.2 Instruction Execution Patterns (9)
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4. Pipelining
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4.2 Parallel-Executability
Instruction Group Instruction
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Table 4.3 Combination of Preceding and Following Instructions
4.3 Issue Rates and Execution Cycles
Table 4.4 Issue Rates and Execution Cycles
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Section 5 Exception Handling
5.1 Summary of Exception Handling
5.2 Register Descriptions
Table 5.2 States of Register in Each Operating Mode
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5.3 Exception Handling Functions
5. Exception Handling
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5.4 Exception Types and Priorities
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5.5 Exception Flow
5. Exception Handling
Figure 5.1 Instruction Execution and Exception Handling
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5. Exception Handling
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Figure 5.2 Example of General Exception Acceptance Order
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5.6 Description of Exceptions
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5.7 Usage Notes
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Section 6 Floating-Point Unit (FPU)
6.1 Features
6.2 Data Formats
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Table 6.2 Floating-Point Ranges
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6.3 Register Descriptions
6. Floating-Point Unit (FPU)
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Figure 6.4 Floating-Point Registers
6.3.2 Floating-Point Status/Control Register (FPSCR)
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6. Floating-Point Unit (FPU)
Figure 6.5 Relation between SZ Bit and Endian
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<Big endian>
<Little endian>
* 1 , * 2 *
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6.4 Rounding
6.5 Floating-Point Exceptions
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6.6 Graphics Support Functions
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Section 7 Memory Management Unit (MMU)
7.1 Overview of MMU
7. Memory Management Unit (MMU)
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Figure 7.1 Role of MMU
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7.2 Register Descriptions
The following registers are related to MMU processing. Table 7.1 Register Configuration
Table 7.2 Register States in Each Processing State
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7.2.6 Page Table Entry Assistance Register (PTEA)
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7.3 TLB Functions (TLB Compatible Mode; MMUCR.ME = 0)
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7. Memory Management Unit (MMU)
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7. Memory Management Unit (MMU)
Figure 7.9 Flowchart of Memory Access Using UTLB (TLB Compatible Mode)
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7. Memory Management Unit (MMU)
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Figure 7.10 shows a flowchart of a memory access using the ITLB.
Figure 7.10 Flowchart of Memory Access Using ITLB (TLB Compatible Mode)
7.4 TLB Functions (TLB Extended Mode; MMUCR.ME = 1)
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7. Memory Management Unit (MMU)
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Figure 7.13 ITLB Configuration (TLB Extended Mode)
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7. Memory Management Unit (MMU)
Figure 7.14 Flowchart of Memory Access Using UTLB (TLB Extended Mode)
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7. Memory Management Unit (MMU)
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Figure 7.15 is a flowchart of memory access using the ITLB in TLB extended mode.
Figure 7.15 Flowchart of Memory Access Using ITLB (TLB Extended Mode)
7.5 MMU Functions
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The operation of the LDTLB instruction is shown in figures 7.16 and 7.17.
Figure 7.16 Operation of LDTLB Instruction (TLB Compatible Mode)
7. Memory Management Unit (MMU)
PTEH PTEL
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MMUCR
Entry specification
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7.6 MMU Exceptions
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7.7 Memory-Mapped TLB Configuration
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7. Memory Management Unit (MMU)
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Figure 7.24 Memory-Mapped UTLB Data Array 1 (TLB Extended Mode)
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7.8 32-Bit Address Extended Mode
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7. Memory Management Unit (MMU)
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Bit Bit Name
Figure 7.28 Memory-Mapped PMB Address Array
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7.9 32-Bit Boot Function
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7.10 Usage Notes
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Section 8 Caches
8.1 Features
8. Caches
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Figure 8.1 Configuration of Operand Cache (Cache size = 32 Kbytes)
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8.2 Register Descriptions
The following registers are related to cache. Table 8.3 Register Configuration
Table 8.4 Register States in Each Processing State
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8.3 Operand Cache Operation
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8.4 Instruction Cache Operation
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8.5 Cache Operation Instruction
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8.6 Memory-Mapped Cache Configuration
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8.7 Store Queues
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8.8 Notes on Using 32-Bit Address Extended Mode
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Section 9 On-Chip Memory
9.1 Features
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9.2 Register Descriptions
The following registers are related to the on-chip memory. Table 9.4 Register Configuration
Table 9.5 Register States in Each Processing Mode
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9.3 Operation
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9.4 On-Chip Memory Protective Functions
9.5 Usage Notes
9.6 Note on Using 32-Bit Address Extended Mode
Section 10 Interrupt Controller (INTC)
10.1 Features
10. Interrupt Controller (INTC)
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Figure 10.1 shows a block diagram of the INTC.
Peripheral bus
Figure 10.1 Block Diagram of INTC
10. Interrupt Controller (INTC)
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The details of the input control circuit of figure 10.1 are shown in figure 10.2.
Figure 10.2 Input Control Circuit for the Interrupt Requested from the External Pin
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10.2 Input/Output Pins
Table 10.2 shows the pin configuration. Table 10.2 INTC Pin Configuration
10.3 Register Descriptions
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Table 10.4 Register States in Each Operating Mode
Note: * initial values of ICR0.NMIL and NMIFCR.NMIL depend on the level input to the NMI pin.
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Table 10.5 Interrupt Request Sources and INT2PRI0 to INT2PRI9
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(1) INT2B0: Detailed Interrupt Sources for the TMU
(2) INT2B1: Detailed Interrupt Sources for the SCIF
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(3) INT2B2: Detailed Interrupt Sources for the DMAC
(4) INT2B3: Detailed Interrupt Sources for the PCIC
(5) INT2B4: Detailed Interrupt Sources for the MMCIF
(6) INT2B5: Detailed Interrupt Sources for the FLCTL
(7) INT2B6: Detailed Interrupt Sources for the GPIO
(8) INT2B7: Detailed Interrupt Sources for the GDTA
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10.4 Interrupt Sources
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10. Interrupt Controller (INTC)
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Table 10.13 Interrupt Exception Handling and Priority
10. Interrupt Controller (INTC)
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10. Interrupt Controller (INTC)
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10. Interrupt Controller (INTC)
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10. Interrupt Controller (INTC)
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10. Interrupt Controller (INTC)
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10.5 Operation
10. Interrupt Controller (INTC)
Figure 10.5 Flowchart of Interrupt Operation
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10.6 Interrupt Response Time
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10.7 Usage Notes
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Section 11 Local Bus State Controller (LBSC)
11.1 Features
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11. Local Bus State Controller (LBSC)
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Figure 11.1 shows a block diagram of the LBSC.
Figure 11.1 Block Diagram of LBSC
11.2 Input/Output Pins
Table 11.1 shows the LBSC pin configuration. Table 11.1 Pin Configuration
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11.3 Overview of Areas
Table 11.2 LBSC External Memory Space Map
Figure 11.3 Local Bus Memory Space Allocation
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Table 11.4 PCMCIA Support Interface
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11.4 Register Descriptions
Note: Do not access with except the specified access size.
Table 11.5 Register Configuration (2)
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11.5 Operation
11. Local Bus State Controller (LBSC)
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Table 11.6 64-Bit External Device/Big Endian Access and Data Alignment (1)
Table 11.7 64-Bit External Device/Big Endian Access and Data Alignment (2)
Table 11.8 32-Bit External Device/Big-Endian Access and Data Alignment
Table 11.9 16-Bit External Device/Big-Endian Access and Data Alignment
Table 11.10 8-Bit External Device/Big-Endian Access and Data Alignment
11. Local Bus State Controller (LBSC)
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Table 11.11 64-Bit External Device/Little Endian Access and Data Alignment (1)
Table 11.12 64-Bit External Device/Little Endian Access and Data Alignment (2)
Table 11.13 32-Bit External Device/Little-Endian Access and Data Alignment
Table 11.14 16-Bit External Device/Little-Endian Access and Data Alignment
Table 11.15 8-Bit External Device/Little-Endian Access and Data Alignment
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11. Local Bus State Controller (LBSC)
Figure 11.5 Basic Timing of SRAM Interface
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11. Local Bus State Controller (LBSC)
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Figure 11.6 Example of 32-Bit Data Width SRAM Connection
11. Local Bus State Controller (LBSC)
Figure 11.7 Example of 16-Bit Data Width SRAM Connection
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11. Local Bus State Controller (LBSC)
Figure 11.9 SRAM Interface Wait Timing (Software Wait Only)
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11. Local Bus State Controller (LBSC)
Figure 11.11 SRAM Interface Wait Timing (Read-Strobe/Write-Strobe Timing Setting)
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Figure 11.12 Burst ROM Basic Timing
Figure 11.13 Burst ROM Wait Timing
11. Local Bus State Controller (LBSC)
Figure 11.14 Burst ROM Wait Timing
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Table 11.16 Relationship between Address and CE when Using PCMCIA Interface
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Legend:
: Don't care L: Low level H: High level
11. Local Bus State Controller (LBSC)
Figure 11.16 Example of PCMCIA Interface
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Figure 11.17 Basic Timing for PCMCIA Memory Card Interface
11. Local Bus State Controller (LBSC)
Figure 11.18 Wait Timing for PCMCIA Memory Card Interface
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11. Local Bus State Controller (LBSC)
Figure 11.19 Basic Timing for PCMCIA I/O Card Interface
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11. Local Bus State Controller (LBSC)
Figure 11.20 Wait Timing for PCMCIA I/O Card Interface
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11. Local Bus State Controller (LBSC)
Figure 11.21 Dynamic Bus Sizing Timing for PCMCIA I/O Card Interface
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11. Local Bus State Controller (LBSC)
Figure 11.37 Example of Byte Control SRAM with 64-Bit Data Width
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Figure 11.38 Basic Read Cycle of Byte Control SRAM (No Wait)
11. Local Bus State Controller (LBSC)
Figure 11.39 Wait State Timing of Byte Control SRAM
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Figure 11.40 Wait State Timing of Byte Control SRAM (One Internal Wait + One External Wait)
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Figure 11.41 Wait Cycles between Access Cycles (Access Size Is 4 Bytes)
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11. Local Bus State Controller (LBSC)
Figure 11.42 Arbitration Sequence
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Section 12 DDR2-SDRAM Interface (DBSC2)
12.1 Features
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12. DDR2-SDRAM Interface (DBSC2)
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Figure 12.1 shows a block diagram of the DBSC2.
Figure 12.1 Block Diagram of the DBSC2
12.2 Input/Output Pins
Table 12.1 shows the pin configuration of the DBSC2. Table 12.1 Pin Configuration of the DBSC2
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Notes: 1. SDRAM pins s hould be connected as shown below.
2. SDRAM pins should be connected as shown below.
3. SDRAM pins should be connected as shown below.
4. SDRAM pins should be connected as shown below.
5. SDRAM pins should be connected as shown below.
6. SDRAM pins should be connected as shown below.
12.3 Data Alignment
12. DDR2-SDRAM Interface (DBSC2)
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Figure 12.2 Burst Access Operation
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Table 12.6 Data Alignment for Access in Big Endian when External Data Bus Width Is Set to 32 Bits
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Table 12.8 Data Alignment for Access in Big Endian when External Data Bus Width Is Set to 16 Bits
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16-byte read/write access (a total of one command is issued)
32-byte write access (a total of two commands are issued)
32-byte read access (a total of two commands are issued)
12.4 Register Descriptions
Table 12.9 DBSC2 Register Configuration
Table 12.10 Register Status in each Processing Mode
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12.5 DBSC2 Operation
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Figure 12.14 tRP, tRCD, CL, and tRAS
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12. DDR2-SDRAM Interface (DBSC2)
Figure 12.21 ODT Control Signal when CL = 4
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Section 13 PCI Controller (PCIC)
13.1 Features
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13.2 Input/Output Pins
Table 13.1 shows the pin configuration of the PCIC. Table 13.1 Signal Descriptions
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13.3 Register Descriptions
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Table 13.3 Register States in Each Processing Mode
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(2) PCI Device ID Register (PCIDID) This field defines the PCI device ID.
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(9) PCI Cache Line Size Register (PCICLS)
(10) PCI Latency Timer Register (PCILTM)
(11) PCI Header Type Register (PCIHDR)
(12) PCI BIST Register (PCIBIST)
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(19) PCI Interrupt Line Register (PCIINTLINE)
(20) PCI Interrupt Pin Register (PCIINTPIN)
(21) Minimum Grant Register (PCIMINGNT) This register is not programmable.
(22) Maximum Latency Register (PCIMAXLAT) This register is not programmable.
(23) PCI Capability Identifier Register (PCICID)
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(4) PCI Local Address Register 0 (PCILAR0) See section 13.4.3 (2), Accessing PCI Memory Space.
(5) PCI Local Address Register 1 (PCILAR1) See section 13.4.3 (2), Accessing PCI Memory Space.
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(7) PCI Interrupt Mask Register (PCIIMR) This register is the mask register for PCIIR.
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13.4 Operation
13.4.1 Supported PCI Commands Table 13.4 Supported PCI Commands
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13. PCI Controller (PCIC)
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Figure 13.7 Endian Conversion from SuperHyway Bus to PCI Bus (Non-Byte Swapping: TBS = 0)
13. PCI Controller (PCIC)
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Figure 13.8 Endian Conversion from SuperHyway Bus to PCI Local Bus (Byte Swapping: TBS = 1)
13. PCI Controller (PCIC)
Figure 13.9 Data Alignments for SuperHyway Bus and PCI Bus
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Figure 13.12 I/O Access from PCI Bus to SuperHyway Bus
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Figure 13.13 Endian Conversion from PCI Bus to SuperHyway Bus (Non-Byte Swapping: TBS = 0)
13. PCI Controller (PCIC)
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Figure 13.14 Endian Conversion from PCI Bus to SuperHyway Bus (Byte Swapping: TBS = 1)
13. PCI Controller (PCIC)
Figure 13.15 Data Alignments for SuperHyway Bus and PCI Bus
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13. PCI Controller (PCIC)
Figure 13.20 Master Read Cycle in Host Mode (Single)
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13. PCI Controller (PCIC)
Figure 13.21 Master Write Cycle in Normal Mode (Burst)
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13. PCI Controller (PCIC)
Figure 13.22 Master Read Cycle in Normal Mode (Burst)
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13. PCI Controller (PCIC)
Figure 13.23 Target Read Cycle in Normal Mode (Single)
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13. PCI Controller (PCIC)
Figure 13.24 Target Write Cycle in Normal Mode (Single)
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13. PCI Controller (PCIC)
Figure 13.25 Target Memory Read Cycle in Host Mode (Burst)
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13. PCI Controller (PCIC)
Figure 13.26 Target Memory Write Cycle in Host Mode (Burst)
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13. PCI Controller (PCIC)
Figure 13.28 Target Memory Read Cycle in Host Bus Bridge Mode (Burst, with Stepping)
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Section 14 Direct Memory Access Controller (DMAC)
14.1 Features
14. Direct Memory Access Controller (DMAC)
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Figure 14.1 shows a block diagram of the DMAC.
SuperHyway bus
Figure 14.1 Block Diagram of DMAC
14.2 Input/Output Pins
14. Direct Memory Access Controller (DMAC)
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14.3 Register Descriptions
Table 14.2 shows the register configuration. Table 14.2 Register Configuration of the DMAC (1)
14. Direct Memory Access Controller (DMAC)
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Table 14.2 Register Configuration of the DMAC (2)
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DMARS4
DMARS5
DMARS0
DMARS1
DMARS2
DMARS3
DMARS4
DMARS5
Table 14.3 List of Transfer Request Sources
14.4 Operation
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Table 14.8 List of On-Chip Peripheral Module Request Modes
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14. Direct Memory Access Controller (DMAC)
Figure 14.2 Round-Robin Mode (Example of Channels 0 to 5)
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Table 14.10 DMA Transfer Directions for On-Chip Peripheral Module Request*2*3
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14. Direct Memory Access Controller (DMAC)
Figure 14.10 Bus Mode and Channel Priority in Priority Fixed Mode
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Figure 14.11 Flowchart of DMA Transfer
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CLKOUT
Figure 14.19 Example of DREQ Input Detection in Burst Mode Edge Detection
Bus cycle DREQ (Rising edge) DRAK (High-active) DACK (High-active)
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14.5 DMAC Interrupt Sources
14.6 Usage Notes
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Section 15 Clock Pulse Generator (CPG)
15.1 Features
15. Clock Pulse Generator (CPG)
Figure 15.1 Block Diagram of the CPG
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15.2 Input/Output Pins
Table 15.1 shows the CPG pin configuration. Table 15.1 CPG Pin Configuration
15.3 Clock Operating Modes
15. Clock Pulse Generator (CPG)
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15.4 Register Descriptions
Note: * For details on the standby control registers, see section 17, Power-Down Mode.
Table 15.6 Register State in Each Processing Mode
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15.5 Calculating the Frequency
15.6 How to Change the Frequency
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Table 15.8 Selectable Combinations of Clock Frequency (CPU Clock: 1/2, DDR Clock: 1/4)
Table 15.9 Selectable Combinations of Clock Frequency (CPU Clock: 1/4, DDR Clock: 1/4)
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Table 15.10 Selectable Combinations of Clock Frequency (CPU Clock: 1/2, DDR Clock: 1/6)
Table 15.11 Selectable Combinations of Clock Frequency (CPU Clock: 1/6, DDR Clock: 1/6)
15.7 Notes on Designing Board
15. Clock Pulse Generator (CPG)
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Figure 15.5 Note on Using a PLL Oscillator Circuit
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Section 16 Watchdog Timer and Reset (WDT)
16.1 Features
16. Watchdog Timer and Reset (WDT)
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Figure 16.1 is a block diagram of the WDT.
Figure 16.1 Block Diagram of WDT
16.2 Input/Output Pins
Table 16.1 shows the pin configuration of the WDT module. Table 16.1 Pin Configuration
16.3 Register Descriptions
Table 16.3 Register States in Each Operating Mode
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16.4 Operation
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16.5 Status Pin Change Timing during Reset
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Section 17 Power-Down Mode
17.1 Features
17. Power-Down Mode
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Table 17.1 States of Power-Down Modes
17.2 Input/Output Pins
Table 17.2 shows the pins related to power-down mode. Table 17.2 Pin Configuration
17.3 Register Descriptions
Table 17.4 Register States of CPG in Each Processing Mode
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17.4 Sleep Mode
17.5 Deep Sleep Mode
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17.6 Module Standby Functions
17.7 Timing of the Changes on the STATUS Pins
17.8 DDR-SDRAM Power Supply Backup
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Section 18 Timer Unit (TMU)
18.1 Features
18. Timer Unit (TMU)
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Figure 18.1 shows a block diagram of the TMU.
Figure 18.1 Block Diagram of TMU
18.2 Input/Output Pins
18.3 Register Descriptions
Tables 18.2 and 18.3 show the TMU register configuration. Table 18.2 Register Configuration (1)
Table 18.3 Register Configuration (2)
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TCR2
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18.4 Operation
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18.5 Interrupts
18.6 Usage Notes
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Section 19 Display Unit (DU)
19.1 Features
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19. Display Unit (DU)
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Figure 19.1 shows a block diagram of the display unit (DU).
Legend: B: byte b: bit w: word
Figure 19.1 Block Diagram of the Display Unit (DU)
19.2 Input/Output Pins
19.3 Register Descriptions
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Table 19.2 Register Configuration
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Table 19.3 Status of Registers in Each Processing Mode
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Initial Value R/W
Internal Update Description
9, 8 PnBRSL 0 R/W Yes
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Bit Bit Name
Initial Value R/W
Internal Update Description 4 to 0 FRQSEL 0 R/W None
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19.4 Operation
Table 19.4 Display Functions of Planes
19. Display Unit (DU)
Figure 19.2 Block Diagram of Plane Configuration and Superpositioning
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Table 19.6 Memory Parameter/ Monitor Parameter Setting Registers
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The arrangement of data in memory is as follows.
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UYVY format
YUYV format
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Endian conversion in each of the units indicated below is shown in figure 19.4.
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Figure 19.4 Endian Conversion
Data
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Table 19.12 Transparent Color Specification Registers
EOR Operation: EOR operation of the specified plane with the lower plane is performed.
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19. Display Unit (DU)
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Figure 19.8 YC Data Contention
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19.5 Display Control
Table 19.13 Variables Defined in Display Screen
Table 19.14 Correspondence Table of Settings of Display Timing Generation Registers
19. Display Unit (DU)
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Figure 19.14 CSYNC Timing Chart (Non-Interlaced Mode, First Half of Interlace Frame)
19. Display Unit (DU)
Figure 19.15 CSYNC Timing Chart (Last Half of Interlace Frame)
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19. Display Unit (DU)
Figure 19.16 Example of Display in Each Scan Mode
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19. Display Unit (DU)
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VDS - HC/2
Figure 19.18 Display in Interlaced Method
VDS + HC/2
VDS
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19.6 Power-Down Sequence
Section 20 Graphics Data Translation Accelerator (GDTA)
20.1 Features
20. Graphics Data Translation Accelerator (GDTA)
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Figure 20.1 shows the GDTA block diagram.
Figure 20.1 GDTA Block Diagram
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20.2 GDTA Address Space
20.3 Register Descriptions
Table 20.2 GDTA Register Configuration (CL Block)
Table 20.3 GDTA Register Configuration (MC Block)
Table 20.4 GDTA Register States in Each Processing Mode (GDTA Common Registers)
Table 20.5 GDTA States in Each Processing Mode (CL Block)
Table 20.6 GDTA States in Each Processing Mode (MC Block)
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A Table of CL_DA Register Settings And Output Data Alignment
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20. Graphics Data Translation Accelerator (GDTA)
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20.4 GDTA Operation
Figure 20.3 YUYV Conversion Functions
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20. Graphics Data Translation Accelerator (GDTA)
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Invalid data
Figure 20.4 ARGB Conversion Functions
Frame height
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20. Graphics Data Translation Accelerator (GDTA)
Figure 20.5 CL Processing Procedure
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Frame height
Figure 20.6 Outline of Estimated Image Generation Function
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20. Graphics Data Translation Accelerator (GDTA)
Figure 20.7 MC Processing Procedure
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20.5 Interrupt Processing
20.6 Data Alignment
20. Graphics Data Translation Accelerator (GDTA)
Figure 20.8 Data Alignment Conversion Pattern
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20.7 Usage Notes
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Section 21 Serial Communication Interface with FIFO (SCIF)
21.1 Features
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21. Serial Communication Interface with FIFO (SCIF)
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21. Serial Communication Interface with FIFO (SCIF)
Figure 21.2 SCIF0_RTS Pin
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21. Serial Communication Interface with FIFO (SCIF)
Figure 21.3 SCIF0_CTS Pin
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Figure 21.4 SCIFn_SCK Pin (n = 0 to 5)
Peripheral bus
Figure 21.5 SCIFn_TXD Pin (n = 0 to 5)
Legend: SPTRW: Write to SCSPTR
SCIFn_TXD
21.2 Input/Output Pins
21. Serial Communication Interface with FIFO (SCIF)
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21.3 Register Descriptions
21. Serial Communication Interface with FIFO (SCIF)
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21. Serial Communication Interface with FIFO (SCIF)
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Table 21.2 Register Configuration (2)
21. Serial Communication Interface with FIFO (SCIF)
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21. Serial Communication Interface with FIFO (SCIF)
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21.3.13 Line Status Register n (SCLSR)
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21.4 Operation
Table 21.4 SCSMR Settings for Serial Transfer Format Selection
Table 21.5 SCSMR and SCSCR Settings for SCIF Clock Source Selection
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SCSMR Settings Serial Transfer Format and Frame Length
Legend: S: Start bit STOP: Stop bit P: Parity bit
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21. Serial Communication Interface with FIFO (SCIF)
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Figure 21.8 shows a sample SCIF initialization flowchart.
Figure 21.8 Sample SCIF Initialization Flowchart
21. Serial Communication Interface with FIFO (SCIF)
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Figure 21.9 Sample Serial Transmission Flowchart
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21. Serial Communication Interface with FIFO (SCIF)
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Figure 21.10 shows an example of the operation for transmission in asynchronous mode.
Figure 21.11 shows an example of the operation when modem control is used.
Figure 21.11 Example of Operation Using Modem Control (SCIF_CTS) (Only in Channel 0)
21. Serial Communication Interface with FIFO (SCIF)
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Figure 21.12 Sample Serial Reception Flowchart (1)
21. Serial Communication Interface with FIFO (SCIF)
Figure 21.12 Sample Serial Reception Flowchart (2)
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21. Serial Communication Interface with FIFO (SCIF)
Figure 21.16 Sample SCIF Initialization Flowchart
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Figure 21.17 Sample Serial Transmission Flowchart
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Figure 21.19 Sample Serial Reception Flowchart (1)
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21. Serial Communication Interface with FIFO (SCIF)
Figure 21.20 Example of SCIF Reception Operation
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21. Serial Communication Interface with FIFO (SCIF)
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Figure 21.21 Sample Flowchart for Transmitting/Receiving Serial Data
21.5 SCIF Interrupt Sources and the DMAC
Table 21.7 SCIF Interrupt Sources
21.6 Usage Notes
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Section 22 Serial I/O with FIFO (SIOF)
22.1 Features
22. Serial I/O with FIFO (SIOF)
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Figure 22.1 shows a block diagram of the SIOF.
Figure 22.1 Block Diagram of SIOF
22.2 Input/Output Pins
Table 22.1 shows the pin configuration. Table 22.1 Pin Configuration
22.3 Register Descriptions
Table 22.3 Register States in Each Operating Mode
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Table 22.4 shows the operation in each transfer mode. Table 22.4 Operation in Each Transfer Mode
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22.4 Operation
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22. Serial I/O with FIFO (SIOF)
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Figure 22.9 Example of Transmit Operation in Master Mode
22. Serial I/O with FIFO (SIOF)
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Figure 22.10 Example of Receive Operation in Master Mode
22. Serial I/O with FIFO (SIOF)
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Figure 22.11 Example of Transmit Operation in Slave Mode
No. 1 2 3 4
Flowchart SIOF Settings SIOF Operation
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22. Serial I/O with FIFO (SIOF)
Figure 22.12 Example of Receive Operation in Slave Mode
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No. 1 2 3 4
Flowchart SIOF Settings SIOF Operation
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22. Serial I/O with FIFO (SIOF)
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SYNCDL = 1
Figure 22.13 Transmit and Receive Timing (8-Bit Monaural Data (1))
22. Serial I/O with FIFO (SIOF)
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SYNCDL = 1
Figure 22.15 Transmit and Receive Timing (16-Bit Monaural Data)
22. Serial I/O with FIFO (SIOF)
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SIOF_TXD
Figure 22.17 Transmit and Receive Timing (16-Bit Stereo Data (2))
SIOF_RXD
SIOF_SCK
SIOF_SYNC
22. Serial I/O with FIFO (SIOF)
Figure 22.19 Transmit and Receive Timing (16-Bit Stereo Data (4))
22. Serial I/O with FIFO (SIOF)
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Figure 22.20 Transmit and Receive Timing (16-Bit Stereo Data)
Section 23 Serial Peripheral Interface (HSPI)
23.1 Features
23. Serial Peripheral Interface (HSPI)
Rev.1.00 Jan. 10, 2008 Page 1152 of 1658 REJ09B0261-0100
Figure 23.1 is a block diagram of the HSPI.
Figure 23.1 Block Diagram of HSPI
23.2 Input/Output Pins
The input/output pins of the HSPI is shown in table 23.1. Table 23.1 Pin Configuration
23.3 Register Descriptions
Table 23.2 Register Configuration (1)
Table 23.3 Register Configuration (2)
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23.4 Operation
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23. Serial Peripheral Interface (HSPI)
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Figure 23.5 Timing Conditions when FBS = 1
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Section 24 Multimedia Card Interface (MMCIF)
24.1 Features
Figure 24.1 shows a block diagram of the MMCIF.
Figure 24.1 Block Diagram of MMCIF
24.2 Input/Output Pins
Table 24.1 summarizes the pins of the MMCIF. Table 24.1 Pin Configuration
24.3 Register Descriptions
Table 24.2 shows the MMCIF register configuration. Table 24.2 Register Configuration (1)
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Table 24.3 Register Configuration (2)
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(1) CMDR0 to CMDR4
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(2) INTCR1
(3) INTCR2
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(2) INTSTR1
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(3) INTSTR2
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(1) RSPR0 to RSPR16
(2) RSPRD
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24.4 Operation
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24. Multimedia Card Interface (MMCIF)
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24. Multimedia Card Interface (MMCIF)
Figure 24.7 Example of Operational Flow for Commands without Data Transfer
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Figure 24.9 Example of Command Sequence for Commands with Read Data (Block Size > FIFO Size)
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Figure 24.10 Example of Command Sequence for Commands with Read Data (Multiple Block Transfer)
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Figure 24.11 Example of Command Sequence for Commands with Read Data (Stream Transfer)
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Figure 24.12 Example of Operational Flow for Commands with Read Data (Single Block Transfer)
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Figure 24.14 Example of Operational Flow for Commands with Read Data (Stream Transfer)
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Figure 24.15 Example of Command Sequence for Commands with Write Data (Block Size FIFO Size)
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Figure 24.16 Example of Command Sequence for Commands with Write Data (Block Size > FIFO Size)
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Figure 24.17 Example of Command Sequence for Commands with Write Data (Multiple Block Transfer)
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Figure 24.18 Example of Command Sequence for Commands with Write Data (Stream Transfer)
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Figure 24.19 Example of Operational Flow for Commands with Write Data (Single Block Transfer)
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24. Multimedia Card Interface (MMCIF)
Legend:
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24. Multimedia Card Interface (MMCIF)
Legend:
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24. Multimedia Card Interface (MMCIF)
Figure 24.21 Example of Operational Flow for Commands with Write Data (Stream Transfer)
24.5 MMCIF Interrupt Sources
24.6 Operations when Using DMA
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24. Multimedia Card Interface (MMCIF)
Figure 24.22 Example of Read Sequence Flow (Single Block Transfer)
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24. Multimedia Card Interface (MMCIF)
Figure 24.23 (1) Example of Read Sequence Flow (Open-ended Multiple Block Transfer)
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24. Multimedia Card Interface (MMCIF)
Figure 24.23 (2) Example of Read Sequence Flow (Open-ended Multiple Block Transfer)
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24. Multimedia Card Interface (MMCIF)
Figure 24.23 (3) Example of Read Sequence Flow (Pre-defined Multiple Block Transfer)
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24. Multimedia Card Interface (MMCIF)
Figure 24.23 (4) Example of Read Sequence Flow (Pre-defined Multiple Block Transfer)
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Legend: n (DTI): Number of data transfer end interrupts (DTI) from the start of read sequence
1 2
24. Multimedia Card Interface (MMCIF)
Figure 24.24 Example of Operational Flow for Stream Read Transfer
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24. Multimedia Card Interface (MMCIF)
Figure 24.26 (1) Example of Write Sequence Flow (Single Block Transfer)
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24. Multimedia Card Interface (MMCIF)
Figure 24.26 (2) Example of Write Sequence Flow (Single Block Transfer)
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24. Multimedia Card Interface (MMCIF)
Figure 24.27 (1) Example of Write Sequence Flow (Open-ended Multiple Block Transfer)
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24. Multimedia Card Interface (MMCIF)
Figure 24.27 (2) Example of Write Sequence Flow (Open-ended Multiple Block Transfer)
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24. Multimedia Card Interface (MMCIF)
Figure 24.27 (3) Example of Write Sequence Flow (Pre-defined Multiple Block Transfer)
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24. Multimedia Card Interface (MMCIF)
Figure 24.27 (4) Example of Write Sequence Flow (Pre-defined Multiple Block Transfer)
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Legend: n (DRPI): Number of data response interrupts (DRPI) from the start of write sequence
24. Multimedia Card Interface (MMCIF)
Figure 24.28 Example of Operational Flow for Stream Write Transfer
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24.7 Register Accesses with Little Endian Specification
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Section 25 Audio Codec Interface (HAC)
25.1 Features
25. Audio Codec Interface (HAC)
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Figure 25.1 shows a block diagram of the HAC.
Peripheral bus
Figure 25.1 Block Diagram
25.2 Input/Output Pins
Table 25.1 describes the HAC pin configuration. Table 25.1 Pin Configuration
25.3 Register Descriptions
Table 25.2 Register Configuration (2)
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In 16-bit packed DMA mode, HACPCML is defined as follows:
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25.4 AC 97 Frame Slot Structure
Figure 25.2 AC97 Frame Slot Structure Table 25.3 AC97 Transmit Frame Structure
Table 25.4 AC97 Receive Frame Structure
25.5 Operation
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25.5.5 Initialization Sequence Figure 25.3 shows an example of the initialization sequence.
Figure 25.3 Initialization Sequence
25. Audio Codec Interface (HAC)
Figure 25.4 Sample Flowchart for Off-Chip Codec Register Write
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25. Audio Codec Interface (HAC)
Figure 25.5 Sample Flowchart for Off-Chip Codec Register Read (1)
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25. Audio Codec Interface (HAC)
Figure 25.6 Sample Flowchart for Off-Chip Codec Register Read (2)
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25. Audio Codec Interface (HAC)
Figure 25.7 Sample Flowchart for Off-Chip Codec Register Read (3)
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Section 26 Serial Sound Interface (SSI) Module
26.1 Features
26. Serial Sound Interface (SSI) Module
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Figure 26.1 is a block diagram of the SSI module.
Peripheral bus
Figure 26.1 Block Diagram of SSI Module
26.2 Input/Output Pins
Table 26.1 lists the pin configurations relating to the SSI module. Table 26.1 Pin Configuration
26.3 Register Descriptions
Table 26.2 Register Configuration (2)
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26.4 Operation
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Table 26.4 Number of Padding Bits for Each Valid Configuration
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Padding
Figure 26.7 Multi-channel Format (6 Channels with High Padding)
Figure 26.6 Multi-channel Format (4 Channels, No Padding)
Padding
26. Serial Sound Interface (SSI) Module
Padding
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26. Serial Sound Interface (SSI) Module
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(1) Transmission Using DMA Controller
Figure 26.21 Transmission Using DMA Controller
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(2) Transmission using Interrupt Data Flow Control
Figure 26.22 Transmission Using Interrupt Data Flow Control
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(1) Reception Using DMA Controller
Figure 26.23 Reception Using DMA Controller
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(2) Reception Using Interrupt Data Flow Control
Figure 26.24 Reception Using Interrupt Data Flow Control
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26.5 Usage Note
26. Serial Sound Interface (SSI) Module
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Figure 26.25 SSI Transfer Termination and Resumption Timing in Slave Mode
Section 27 NAND Flash Memory Controller (FLCTL)
27.1 Features
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27. NAND Flash Memory Controller (FLCTL)
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Figure 27.1 shows a block diagram of the FLCTL.
Figure 27.1 Block Diagram of FLCTL
27.2 Input/Output Pins
Table 27.1 shows the pin configuration of the FLCTL. Table 27.1 Pin Configuration
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27.3 Register Descriptions
Table 27.3 Register States in Each Processing Mode
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Sector access mode
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27.4 Operation
27. NAND Flash Memory Controller (FLCTL)
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Figure 27.3 Writing Operation Timing for NAND-Type Flash Memory
Figure 27.4 Status Read Operation Timing for NAND-Type Flash Memory
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Figure 27.6 Writing Operation Timing for NAND-Type Flash Memory
Figure 27.7 Status Read Operation Timing for NAND-Type Flash Memory
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Figure 27.9 Example of Sector Number and NAND-Type Flash Memory Address Expansion
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27. NAND Flash Memory Controller (FLCTL)
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27.5 Example of Register Setting
The examples of setting and starting registers in each access mode are shown below.
Figure 27.11 NAND Command Access (Block Erase)
27. NAND Flash Memory Controller (FLCTL)
Figure 27.12 NAND Sector Access (Flash Write) Using DMAC
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27. NAND Flash Memory Controller (FLCTL)
Figure 27.13 NAND Command Access (Flash Read)
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27.6 Interrupt Processing
27.7 DMA Transfer Settings
Section 28 General Purpose I/O Ports (GPIO)
28.1 Features
Table 28.1 Multiplexed Pins Controlled by Port Control Registers
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Pin Name Port GPIO Selectable Module
GPIO Interrupt
28.2 Register Descriptions
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Table 28.2 Register Configuration (2)
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28.3 Usage Example
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Section 29 User Break Controller (UBC)
29.1 Features
29. User Break Controller (UBC)
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Figure 29.1 shows the UBC block diagram.
Figure 29.1 Block Diagram of UBC
29.2 Register Descriptions
The UBC has the following registers. Table 29.1 Register Configuration
Table 29.2 Register Status in Each Processing State
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CBR1
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CRR1
CAR1
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CAMR1
Table 29.3 Settings for Match Data Setting Register
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29.3 Operation Description
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29. User Break Controller (UBC)
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29.4 User Break Debugging Support Function
Figure 29.2 Flowchart of User Break Debugging Support Function
29.5 User Break Examples
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29.6 Usage Notes
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Section 30 User Debugging Interface (H-UDI)
30.1 Features
30. User Debugging Interface (H-UDI)
Figure 30.1 Block Diagram of H-UDI
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30.2 Input/Output Pins
Table 30.1 shows the pin configuration of the H-UDI. Table 30.1 Pin Configuration of H-UDI
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30.3 Register Description
The H-UDI has the following registers. Table 30.2 Register Configuration (1)
Table 30.3 Register Configuration (2)
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Table 30.5 Boundary Scan Register Configuration
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30.4 Operation
30. User Debugging Interface (H-UDI)
Figure 30.2 Sequence to Switch from Boundary-Scan TAP Controller to H-UDI
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30. User Debugging Interface (H-UDI)
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Figure 30.3 Diagram of Transitions of TAP Controller State
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30.5 Usage Notes
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Section 31 Register List
31.1 Register Address List
31. Register List
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Table 31.1 Register Address List
31. Register List
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31.2 States of the Registers in the Individual Operating Modes
31. Register List
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31. Register List
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31. Register List
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31. Register List
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31. Register List
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Table 31.3 States of the Registers in the Individual Operating Modes (2)
31. Register List
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31. Register List
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Table 31.4 States of the Registers in the Individual Operating Modes (3)
31. Register List
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Table 31.5 States of the Registers in the Individual Operating Modes (4)
31. Register List
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31. Register List
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31. Register List
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31. Register List
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31. Register List
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31. Register List
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31. Register List
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Notes: 1. Bits 2 and 0 ar e undefined. 2. Bits 6, 4, 2 and 0 are undefined.
31. Register List
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Table 31.6 States of the Registers in the Individual Operating Modes (5)
31. Register List
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Table 31.7 States of the Registers in the Individual Operating Modes (6)
31. Register List
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Table 31.8 States of the Registers in the Individual Operating Modes (7)
Table 31.9 States of the Registers in the Individual Operating Modes (8)
Section 32 Electrical Characteristics
32.1 Absolute Maximum Ratings
Table 32.1 Absolute Maximum Ratings*1, 2
32.2 DC Characteristics
Table 32.2 DC Characteristics (Ta = 20 to 85/40 to 85C)
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Table 32.3 Permissible Output Currents
Table 32.4 ODT Characteristics
32.3 AC Characteristics
32.3.1 Clock and Control Signal Timing Table 32.6 Clock and Control Signal Timing
Figure 32.1 EXTAL Clock Input Timing
32. Electrical Characteristics
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Figure 32.2 CLKOUT Clock Output Timing (1)
Figure 32.3 CLKOUT Clock Output Timing (2)
32. Electrical Characteristics
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Figure 32.4 Power-On Oscillation Settling Time
CLKOUT output
Figure 32.5 PLL Synchronization Settling Time
EXTAL input
t
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Figure 32.7 Control Signal Timing
Figure 32.8 STATUS Pin Output Timing at Power-On Reset
t
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32. Electrical Characteristics
Figure 32.9 SRAM Bus Cycle: Basic Bus Cycle (No Wait)
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32. Electrical Characteristics
Figure 32.10 SRAM Bus Cycle: Basic Bus Cycle (One Internal Wait Cycle)
Legend
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:
32. Electrical Characteristics
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Legend:
32. Electrical Characteristics
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Legend:
32. Electrical Characteristics
Figure 32.13 Burst ROM Bus Cycle (No Wait)
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Legend:
CLKOUT A25 to A5
A4 to A0
32. Electrical Characteristics
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Legend:
A25 to A5 A4 to A0
32. Electrical Characteristics
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Legend:
A25 to A5 A4 to A0
32. Electrical Characteristics
Figure 32.16 Burst ROM Bus Cycle (One Internal Wait Cycle + One External Wait Cycle)
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Legend:
A25 to A5 A4 to A0
32. Electrical Characteristics
Figure 32.17 PCMCIA Memory Bus Cycle
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Legend:
32. Electrical Characteristics
Figure 32.18 PCMCIA I/O Bus Cycle
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Legend:
32. Electrical Characteristics
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Figure 32.19 PCMCIA I/O Bus Cycle (TED = 1, TEH = 1, One Internal Wait Cycle, with Bus Sizing)
32. Electrical Characteristics
Figure 32.20 MPX Basic Bus Cycle (Read)
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Legend:
32. Electrical Characteristics
Figure 32.21 MPX Basic Bus Cycle (Write)
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Legend:
32. Electrical Characteristics
Figure 32.22 MPX Bus Cycle (Burst Read)
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32. Electrical Characteristics
Figure 32.23 MPX Bus Cycle (Burst Write)
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32. Electrical Characteristics
Figure 32.24 Memory Byte Control SRAM Bus Cycle
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t
32. Electrical Characteristics
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Legend:
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Figure 32.26 MCK Output Clock
32. Electrical Characteristics
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Figure 32.27 Command Signal and MCK Output Clock
Figure 32.28 MDQS Input Timing at Data Read
32. Electrical Characteristics
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MDQS[3:0] (solid line) MDQS[3:0] (dotted line)
Figure 32.29 Restriction of MDQS Input Waveform (Read)
Figure 32.30 MDQS Output Waveform to MCK (Write)
Figure 32.31 MDQS Output Waveform (Write)
MDQS[3:0] (solid line) MDQS[3:0] (dotted line)
HiZ HiZ
Figure 32.32 MDQS and MDQ/MDM Output Waveform (Write)
Figure 32.33 MDQ High-Impedance Time from MDQS (Write)
Figure 32.34 Interrupt Signal Input Timing (1)
32. Electrical Characteristics
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Figure 32.35 Interrupt Signal Input Timing (2)
Figure 32.36 IRQOUT Timing
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32. Electrical Characteristics
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Figure 32.37 PCI Clock Input Timing
Tri-state output
Figure 32.38 PCI Output Signal Timing
0.4V
PCICLK
Figure 32.40 DREQ/DRAK Signal Timing
Figure 32.41 TCLK Input Timing
Figure 32.42 SCIFn_CLK Input Clock Timing
Figure 32.43 Clock Timing in SCIF I/O Synchronous Mode
Figure 32.44 TCK Input Timing
32. Electrical Characteristics
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Figure 32.45 RESET Hold Timing
Figure 32.46 H-UDI Data Transfer Timing
Figure 32.47 Pin Break Timing
32.3.11 GPIO Signal Timing Table 32.16 GPIO Signal Timing
Figure 32.48 GPIO Signal Timing
32.3.12 HSPI Module Signal Timing Table 32.17 HSPI Module Signal Timing
Figure 32.49 HSPI Data Output/Input Timing
32.3.13 SIOF Module Signal Timing Table 32.18 SIOF Module Signal Timing
Figure 32.50 SIOF_MCLK Input Timing
32. Electrical Characteristics
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Figure 32.51 SIOF Transmission/Reception Timing (Master Mode 1, Sampling on Falling Edges)
Figure 32.52 SIOF Transmission/Reception Timing (Master Mode 1, Sampling on Rising Edges)
32. Electrical Characteristics
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Figure 32.53 SIOF Transmission/Reception Timing (Master Mode 2, Sampling on Falling Edges)
Figure 32.54 SIOF Transmission/Reception Timing (Master Mode 2, Sampling on Rising Edges)
32. Electrical Characteristics
Rev.1.00 Jan. 10, 2008 Page 1612 of 1658 REJ09B0261-0100
Figure 32.55 SIOF Transmission/Reception Timing (Slave Mode 1, Slave Mode 2)
32.3.14 MMCIF Module Signal Timing Table 32.19 MMCIF Module Signal Timing
Figure 32.56 MMCIF Transmission Timing
Figure 32.58 HAC Cold Reset Timing
32. Electrical Characteristics
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Figure 32.59 HAC Warm Reset Timing
Figure 32.60 HAC Clock Input Timing
Figure 32.61 HAC Interface Module Signal Timing
32.3.16 SSI Interface Module Signal Timing Table 32.21 SSI Interface Module Signal Timing
Figure 32.62 SSI Clock Input/Output Timing
Figure 32.63 SSI Transmission Timing (1)
32. Electrical Characteristics
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Figure 32.64 SSI Transmission Timing (2)
t
Figure 32.66 SSI Reception Timing (2)
t
SSIn_SCK SSIn_WS SSIn_SDATA
32.3.17 FLCTL Module Signal Timing Table 32.22 NAND-Type Flash Memory Interface Timing
32. Electrical Characteristics
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Figure 32.67 Command Issue Timing of NAND-Type Flash Memory
Figure 32.68 Address Issue Timing of NAND-Type Flash Memory
32. Electrical Characteristics
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Figure 32.69 Data Read Timing of NAND-Type Flash Memory
Figure 32.70 Data Write Timing of NAND-Type Flash Memory
32. Electrical Characteristics
Figure 32.71 Status Read Timing of NAND-Type Flash Memory
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Table 32.24 Display Timing Conditions: VDDQ = 3.3 V 0.3 V, Ta = 40C to +85C, GND = VSSQ = 0 V
Table 32.25 Classification of Pins
Figure 32.72 PCICLK/DCLKIN Clock Input Timing
32. Electrical Characteristics
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Figure 32.73 Display Timing (with Respect to PCICLK/DCLKIN)
Figure 32.74 Display Timing (with Respect to DEVSEL/DCLKOUT)
32.4 AC Characteristic Test Conditions
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B. Mode Pin Settings
Table B.1 Clock Operating Modes with External Pin Combination
Table B.2 Area 0 Memory Type and Bus Width
Table B.3 Endian
Table B.4 Master/Slave
Table B.5 Clock Input
Table B.6 Bus Mode
Table B.7 Boot Address Mode
Table B.8 Mode Control
Table B.9 Mode Control
C. Pin Functions
C.1 Pin States Table C.1 Pin States in Reset, Power-Down State, and Bus-Released State
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C.2 Handling of Unused Pins Table C.2 Treatment of Unused Pins
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D. Turning On and Off Power Supply
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E. Version Registers (PVR, PRR)
Processor Version Register (PVR)
Product Register (PRR)
F. Product Lineup
Table F.1 SH7785 Product Lineup
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Renesas 32-Bit RISC Microcomputer Hardware Manual SH7785
http://www.renesas.com
Page
SH7785 Hardware Manual
