15. Clock Pulse Generator (CPG)
Rev.1.00 Jan. 10, 2008 Page 742 of 1658
REJ09B0261-0100
15.4.2 Frequency Control Register 1 (FRQCR1)
FRQCR1 is a 32-bit readable/writable register that can select the division ratio of divider 2 for the
CPU clock (lck), the SuperHyway clock (SHck), the peripheral clock (Pck), the DDR clock
(DDRck), the bus clock (Bck), the GDTA clock (GAck), the DU clock (DUck), and the RAM
clock (Uck). To check the division ratio of divider 2 for each clock, read FRQMR1. FRQCR1 can
only be accessed in longwords.
FRQCR1 only changes the division ratio of a clock to which a value other than H'0 has been
written. Therefore, set a value other than H'0 in the bit corresponding to the clock for which you
want to change the division ratio. Other bits should be set to H'0.
To change the division ratio of each clock to the value set in FRQCR1, you must set 1 in the
FRQE bit in FRQCR0 to execute the sequence that changes the frequency. After the sequence is
executed, this register is automatically cleared to H'0000 0000.
However, when changing the division ratio of the DDR clock (DDRck), switch SDRAM to the
self-refreshing state. For details on how to switch to or release the self-refreshing state, see section
12, DDR2-SDRAM Interface (DBSC2).
FRQCR1 is initialized by only a power-on reset via the PRESET pin or a WDT overflow.
161718192021222324252627282931 30
0000000000000000
BFC0BFC1BFC2BFC3SFC0SFC1SFC2SFC3UFC0UFC1UFC2UFC3IFC0IFC1IFC3 IFC2
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/W R/W
BIt:
Initial value:
R/W:
01234567891011121315 14
0000000000000000
PFC0PFC1PFC2PFC3S3FC0S3FC1S3FC2S3FC3S2FC0S2FC1S2FC2S2FC3MFC0MFC1MFC3 MFC2
R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/W R/W
BIt:
Initial value:
R/W: