10. Interrupt Controller (INTC)
Rev.1.00 Jan. 10, 2008 Page 286 of 1658
REJ09B0261-0100
(6) Interrupt Mask Register 1 (INTMSK1) INTMSK1 is a 32-bit readable and conditionally writable register that sets masking for IRL interrupt requests. To clear the mask setting for the interrupt, write 1 to the corresponding bit in INTMSKCLR1. Writing 0 to the bits in INTMSK1 has no effect. By reading this register once after writing to this register or after clearing the mask by setting IMTMSKCLR1, the time length necessary for reflecting the register value can be assured (the value read is reflected to the mask status).
161718192021222324252627282931 30
0000000011111111
⎯⎯⎯⎯⎯⎯
⎯⎯⎯⎯
⎯⎯⎯⎯
IM10 IM11
RRRRRRRRRRRRRRR/W R/W
Bit:
Initial value:
R/W:
01234567891011121315 14
0000000000000000
⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯
RRRRRRRRRRRRRRRR
Bit:
Initial value:
R/W:
Bit Name
Initial
Value R/W Description
31 IM10 1 R/W Mask setting for all IRL3 to
IRL0 interrupt sources
when pins IRQ/IRL3 to
IRQ/IRL0 operate as an
encoded interrupt input.
30 IM11 1 R/W Mask setting for all IRL7 to
IRL4 interrupt sources
when pins IRQ/IRL7 to
IRQ/IRL4 operate as an
encoded interrupt input.
[When read]
0: The interrupt is
accepted.
1: The interrupt is
masked.
[When written]
0: No effect
1: Masks the interrupt
29 to 24 ⎯ All 1 R Reserved
These bits are always read as 1. The write value
should always be 1.
23 to 0 ⎯ All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.