32. Electrical Characteristics
Rev.1.00 Jan. 10, 2008 Page 1622 of 1658
REJ09B0261-0100
32.3.18 Display Unit Signal Timing Table 32.23 PCICLK/DCLKIN Signal Timing Conditions: VDDQ = 3.3 V ±0.3 V, Ta = -40°C to + 85°C, GND = VSSQ = 0 V
Item Symbol Min. Typ. Max. Unit Figure
PCICLK/DCLKIN cycle time tDICYC 20 — — ns 32.72
PCICLK/DCLKIN high level width tDCKIH 8 — — ns
PCICLK/DCLKIN low level width tDCKIL 8 — — ns
Table 32.24 Display Timing Conditions: VDDQ = 3.3 V ±0.3 V, Ta = –40°C to +85°C, GND = VSSQ = 0 V
Item Symbol Min. Typ. Max. Unit Figures
Display input control
signal setup time
tDS 5 ns
Display input control
signal hold time
tDH 3 ns
Figure 32.73
(with respect to
PCICLK/
DCLKIN)
DEVSEL/DCLKOUT
output cycle time
tDCYC 20 — — ns
DEVSEL/DCLKOUT
output high level width
tDCKH 6 — — ns
Delay time of display
output control signal
output
tDD -2 8 ns
Display digital data output
delay time
tDD -2 8 ns
Figure 32.74
(with respect to
DEVSEL/
DCLKOUT)
IRDY/HSYNC input low
level width
tEXHLW 4 × tDCYCns Figure 32.75
IRDY/HSYNC input high
level width
tEXHHW 4 × tDCYCns
PCIFRAME/VSYNC input
low level width
tEXVLW 3 × HC tDCYC
LOCK/ODDF setup time 1 tOD1 (ys + yw) × HC tDCYC
LOCK/ODDF setup time 2 tOD2 1 × HC tDCYC