23. Serial Peripheral Interface (HSPI)
Rev.1.00 Jan. 10, 2008 Page 1155 of 1658
REJ09B0261-0100
23.3.1 Control Register (SPCR) SPCR is a 32-bit readable/writable register that controls the transfer data of shift timing and specifies the clock polarity and frequency.
161718192021222324252627282931 30
——
RRRRRRRRRRRRRRRR
Bit:
Initial value:
R/W:
01234567891011121315 14
00000000
CLKC0CLKC1CLKC2CLKC3CLKC4
IDIVCLKPFBS——
0000000000000000
00000000
R/WR/WR/WR/WR/WR/WR/WR/WRRRRRRRR
Bit:
Initial value:
R/W:
Bit Bit Name
Initial
Value R/W Description
31 to 8 All 0 R Reserved
These bits are always read as an undefined value. The
write value should always be 0.
7 FBS 0 R/W First Bit Start
Controls the timing relationship between each bit of
transferred data and the serial clock.
0: The first bit transmitted from the HSPI module is set
up such that it can be sampled by the receiving device at
the first edge of HSPI_CLK specified by the register after
the HSPI_CS pin goes low. Similarly the first received bit
is sampled at the first edge of HSPI_CLK after the
HSPI_CS pin goes low.
1: The first bit transmitted from the HSPI module is set
up such that it can be sampled by the receiving device at
the second edge of HSPI_CLK after the HSPI_CS pin
goes low. Similarly the first received bit is sampled at the
second edge of HSPI_CLK specified by the register after
the HSPI_CS pin goes low.
6 CLKP 0 R/W Serial Clock Polarity
0: HSPI_CLK signal is not inverted and so is low when
inactive.
1: HSPI_CLK signal is inverted and so is high when
inactive.