13. PCI Controller (PCIC)
Rev.1.00 Jan. 10, 2008 Page 629 of 1658
REJ09B0261-0100
(28) PCI PIO Data Register (PCIPDR) By reading or writing to this register, a configuration cycle is generated on the PCI bus. For details, see section 13.4.5 (2), Configuration Space Access.
SH R/W:
PCI R/W:
SH R/W:
PCI R/W:
161718192021222324252627282931 30Bit:
Initial value:
PDR
PDR
01234567891011121315 14Bit:
Initial value:
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R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/W R/W
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R/WR/WR/WR/WR/WR/WR/WR/W
R/WR/WR/WR/WR/WR/WR/W R/W
Bit Bit Name
Initial
Value R/W Description
31 to 0 PDR H'xxxx
xxxx
SH: R/W
PCI:
PCI PIO Data Register
By reading or writing to this register, a configuration
cycle is generated on the PCI bus.