13. PCI Controller (PCIC)
Rev.1.00 Jan. 10, 2008 Page 609 of 1658
REJ09B0261-0100
(11) PCI Arbiter Interrupt Mask Register (PCIAINTM) This register is the mask register for PCIAINT.
SH R/W:
PCI R/W:
SH R/W:
PCI R/W:
161718192021222324252627282931 30Bit:
Initial value:
RRRRRRRRRRRRRRRR
RRRRRRRRRRRRRRRR
0000000000000000
——
R/WCR/WCR/WCR/WCRRRRRRRR/WCR/WCR/WCRR
RRRRRRRRRRRRRRRR
0000000000000000
WDP
EIM
RDP
EIM
MAIMTAI M
MBT
OIM
TBT
OIM
MBIM——
01234567891011121315 14Bit:
Initial value:
Bit Bit Name
Initial
Value R/W Description
31 to 14 All 0 SH: R
PCI: R
Reserved
These bits are always read as 0. The write value
should always be 0.
13 MBIM 0 SH: R/WC
PCI: R
Master-Broken Interrupt Mask
0: MBI disabled (masked)
1: MBI enabled (not masked)
12 TBTOIM 0 SH: R/WC
PCI: R
Target Bus Time-Out Interrupt Mask
0: TBTOI disabled (masked)
1: TBTOI enabled (not masked)
11 MBTOIM 0 SH: R/WC
PCI: R
Master Bus Time-Out Interrupt Mask
0: MBTOI disabled (masked)
1: MBTOI enabled (not masked)
10 to 4 All 0 SH: R
PCI: R
Reserved
These bits are always read as 0. The write value
should always be 0.
3 TAIM 0 SH: R/WC
PCI: R
Target-Abort Interrupt Mask
0: TAI disabled (masked)
1: TAI enabled (not masked)