22. Serial I/O with FIFO (SIOF)
Rev.1.00 Jan. 10, 2008 Page 1121 of 1658
REJ09B0261-0100
Bit Bit Name
Initial
Value R/W Description
7 to 5 RFWM[2:0] 000 R/W Receive FIFO Watermark
000: Issue a transfer request when 1 stage or more of
the receive FIFO are valid.
001: Setting prohibited
010: Setting prohibited
011: Setting prohibited
100: Issue a transfer request when 4 or more stages of
the receive FIFO are valid.
101: Issue a transfer request when 8 or more stages of
the receive FIFO are valid.
110: Issue a transfer request when 12 or more stages
of the receive FIFO are valid.
111: Issue a transfer request when 16 stages of the
receive FIFO are valid.
• A transfer request to the receive FIFO is issued by
the RDREQE bit in SISTR.
• The receive FIFO is always used as 16 stages of
the FIFO regardless of these bit settings.
4 to 0 RFUA[4:0] 00000 R Receive FIFO Usable Area
These bits indicate the number of words that can be
transferred by the CPU or DMAC as B'00000 (empty) to
B'10000 (full).