Rev.1.00 Jan. 10, 2008 Page xiii of xxx
REJ09B0261-0100
8.7 Store Queues...................................................................................................................... 238
8.7.1 SQ Configuration................................................................................................238
8.7.2 Writing to SQ......................................................................................................238
8.7.3 Transfer to External Memory..............................................................................239
8.7.4 Determination of SQ Access Exception..............................................................240
8.7.5 Reading from SQ................................................................................................ 240
8.8 Notes on Using 32-Bit Address Extended Mode............................................................... 241
Section 9 On-Chip Memory.............................................................................................. 243
9.1 Features..............................................................................................................................243
9.2 Register Descriptions......................................................................................................... 246
9.2.1 On-Chip Memory Control Register (RAMCR).................................................. 247
9.2.2 OL memory Transfer Source Address Register 0 (LSA0)..................................248
9.2.3 OL memory Transfer Source Address Register 1 (LSA1)..................................250
9.2.4 OL memory Transfer Destination Address Register 0 (LDA0)..........................252
9.2.5 OL memory Transfer Destination Address Register 1 (LDA1)..........................254
9.3 Operation........................................................................................................................... 256
9.3.1 Instruction Fetch Access from the CPU..............................................................256
9.3.2 Operand Access from the CPU and Access from the FPU................................. 256
9.3.3 Access from the SuperHyway Bus Master Module............................................257
9.3.4 OL Memory Block Transfer............................................................................... 257
9.4 On-Chip Memory Protective Functions.............................................................................260
9.5 Usage Notes....................................................................................................................... 261
9.5.1 Page Conflict...................................................................................................... 261
9.5.2 Access Across Different Pages........................................................................... 261
9.5.3 On-Chip Memory Coherency............................................................................. 261
9.5.4 Sleep Mode......................................................................................................... 262
9.6 Note on Using 32-Bit Address Extended Mode.................................................................262
Section 10 Interrupt Controller (INTC)......................................................................... 263
10.1 Features..............................................................................................................................263
10.1.1 Interrupt Method.................................................................................................266
10.1.2 Interrupt Sources.................................................................................................267
10.2 Input/Output Pins...............................................................................................................272
10.3 Register Descriptions......................................................................................................... 273
10.3.1 External Interrupt Request Registers.................................................................. 277
10.3.2 User Mode Interrupt Disable Function............................................................... 298
10.3.3 On-chip Module Interrupt Priority Registers......................................................300
10.3.4 Individual On-Chip Module Interrupt Source Registers (INT2B0 to INT2B7)..314
10.3.5 GPIO Interrupt Set Register (INT2GPIC).......................................................... 322