26. Serial Sound Interface (SSI) Module
Rev.1.00 Jan. 10, 2008 Page 1301 of 1658
REJ09B0261-0100
26.3.1 Control Register (SSICR) SSICR is a 32-bit readable/writable register that controls interrupts, selects each polarity status, and sets operating mode.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0000000000000
BRENPDTASDTA DELSWSP SPDPSWSDSCKD SCKP MUEN CPEN TRMD EN
CHNL1 CHNL0 DWL2IIENOIEN DIENDMEN UIEN DWL1
CKDV2CKDV1 CKDV0
DWL0 SWL2 SWL1 SWL0
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
1514131211109876543210
R R R R/W R/W R/W R/W R/WR/W R/W R/W R/WR/WR/WR/W R/W
0000000000000000
R/W R/W R/W R/W R/W R/W R/W R/WR/W R/W R/W R/WR/WR/WR/W R/W
Bit Bit Name
Initial
Value R/W Description
31 to 29 0 R Reserved
These bits are always read as an undefined value. The
write value should always be 0.
28 DMEN 0 R/W DMA Enable
Enables or disables the DMA request.
0: DMA request disabled.
1: DMA request enabled.
27 UIEN 0 R/W Underflow Interrupt Enable
0: Underflow interrupt disabled
1: Underflow interrupt enabled
26 OIEN 0 R/W Overflow Interrupt Enable
0: Overflow interrupt disabled
1: Overflow interrupt enabled
25 IIEN 0 R/W Idle Mode Interrupt Enable
0: Idle mode interrupt disabled
1: Idle mode interrupt enabled
24 DIEN 0 R/W Data Interrupt Enable
0: Data interrupt disabled
1: Data interrupt enabled